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Zybo Z720 Ports Connection Question


Go to solution Solved by thinkthinkthink,

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I am currently doing the vertical farming project. And I want to put my Pmod HYGRO and Pmod AQS sensor into the same port JC. I have tried to put my Pmod HYGRO and Pmod AQS into different Pmod ports successfully. Now, I just want to combine these two sensors into one port. 

For example, for port JC. I want the top layer of the port connect to Pmod AQS and the bottom layer of the port to the Pmod HYGRO. 

So what is my first step to do when comes to vivado block design and how am I going to write my Cpp code into Vitis IDE?

I did some primary research on this topic before. I may need to use AXI IIC or something else. Is that true? 

Also, if using AXI IIC, how am I going to connect the Pmod to the AXI IIC and connect the specific pin of Pmod to the specific pin of the port? Thanks in advance. 

Below is my vivado block design so far? 

image.thumb.png.97e5885b0e4861956d79e5a26fb5f572.png

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Posted (edited)

I think I've told you that you can daisy chain both PmodHYGRO and PmodAQS without needing to use both rows on the pmod port of your board.

It would look something like this:

image.thumb.png.d9b4b674498c0cf504b6684accf0fef0.png

(Please don't mind my horrible paint skills.)

And because they have different i2c addresses there would be no conflict when trying to communicate with any of them while they're connected like this.

Their Pmod_out interfaces don't have to be connected together inside the block design because they're going to be physically connected by way of daisy chain, just be careful when you're writing the xdc file and consult the schematics of your board and of the two pmods when in doubt.

Edited by thinkthinkthink
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Thanks so much. Maybe I confuse with meaning of "daisy chain". But what i am worry is how to configurate this into Vivado block design, as well as the coding part when the xsa file in vivado exports to Vitis IDE. Should I use the IP core of AQS and HYGRO for block design? Or Should I use the AXI IIC only? My intern supervisor told me that for port JF i may not need IP Core. But JB to JE need IP core. I am worried that if it works only when it places on JF port because I need to use JF port for my LED and Water pump control. 

Sorry that I am new to FPGA and still catching up with some fundamental knowledges.  

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Posted (edited)

I think based on my understanding, I should draw my block diagram in this way. I connect the AQS to JC port and connect the J2 of the aqs to the J1 of the hygro. 

image.thumb.png.1b30d84c9b8e7d351295a97ff7508de9.png

 

 

Edited by lukelouyu
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