Question

I want to use PmodIOXP to allow both PmodAQS and PmodHYGRO to be connected into the same port in Zybo Z720. However, I do not know how to write my block design in Vivado since there is no IP for PmodIOXP in the vivado-library. Also, what kind of C++ code should I write in my Vitis after I exported my vivado file into Vitis

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The PmodIOXP doesn't necessarily need it's own IP since you can just use one of Xilinx's AXI IIC IP or the IIC inside the ZYNQ processing system by constraining their input/output interface to a Pmod port of your choice on your board according to this pinout (which you can easily find on its Resource Center page):

image.png.2f8b77b5300d43cdc5598d79ee00cd15.png

And at the bottom of the Resource Center page you can even find a link to a demo project done by Analog Devices.

But the most important part is to get familiar with the ADP5589 which is the main component of the PmodIOXP by checking out our Reference Manual and its datasheet at: https://www.analog.com/media/en/technical-documentation/data-sheets/ADP5589.pdf

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13 minutes ago, thinkthinkthink said:

IIC inside the ZYNQ processing system by constraining their input/output interface to a Pmod port of your choice on your board according to this pino

So do you mean that i connect AXI IIC  and other two Pmod sensors according to the pinout. And How am I going to connect two Pmod sensors to connector JC?

image.png

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Actually, now that I think about it the PmodIOXP isn't right for your application since both the PmodHYGRO and the PmodAQS have to communicate with the processing system via the I2C protocol. The outputs of the PmodIOXP are all GPIOs which mean you'd have to get into bit banging territory to obtain proper I2C communication with the other 2 Pmods and this will add more complexity to your project but it should be a fun challenge.

What I mean by "constraining their input/output interface to a Pmod port of your choice on your board" is adding this xdc constraints file into your project and uncommenting some specific lines like so:

image.png.b7bdd16fc2259b273705705511037002.png

While my block design looks like this:

image.thumb.png.e22192240920cb4579384b47414fe61e.png

 

Edited by thinkthinkthink
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Thanks for your answer. So is there is a way to connect the Pmod HYGRO and Pmod AQS into the same high-speed Pmod port without using PmodIOXP or the simplest way to achieve this function? If yes, how am I going to do a block design in Vivado. I will continue to figure out the possibility of using PmodIOXP to achieve the result I want. 

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The PmodTPH2 and some female to female cables should probably do the trick but make sure PmodHYGRO and PmodAQS have different i2c addresses.

Edit: Actually from what I can see you can daisy chain the PmodHYGRO and the PmodAQS by connecting one into the other without needing additional connectors/cables since their SDA and SCL pinout match perfectly.

Edited by thinkthinkthink
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image.thumb.png.9f92fe0305f13ca948aaca8d33e97c94.png

This is how I draw the block design, I don't know how to connect the AQS and HYGRO IP core into AXI IIC. Is it like pin3 (SCL) of the AQS/HYGRO connect to scl_i/scl_o/scl_t and pin 4 of the AQS/HYGRO connect to sda_i/sda_o/sda_t? Any connection for AXI_LITE_TMR (HYGRO) and AXI_LITE_IIC (HYGRO & AQS)? And is the iic_rtl already represents the connector JC?

I have written

set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33     } [get_ports { iic_rtl_scl_io }]; #IO_L1P_T0_34 Sch=jc_p[2]              
set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33     } [get_ports { iic_rtl_sda_io }]; #IO_L1N_T0_34 Sch=jc_n[2] 

into my newly-added ZYBO master xdc file. 

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ALSO, for this part

Edit: Actually from what I can see you can daisy chain the PmodHYGRO and the PmodAQS by connecting one into the other without needing additional connectors/cables since their SDA and SCL pinout match perfectly.

Will it affect the block design in Vivado and Vitis as well? 

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I honestly think you don't need to have the PmodHYGRO and PmodAQS IPs present in the block design anymore since you'll do all the work with the AXI IIC IP so they can be removed.

What you have to pay attention to though is at the way you're gonna connect them to the Pmod port on your board and that's where the xdc file comes in. Make sure everything is correct by also checking the schematics of your Zybo (specifically the first page where it shows the Pmod ports) and your PmodHYGRO and PmodAQS.

Also, at first try to learn and get experience by working with the 2 pmods on two different ports on your board and make sure you can get them working properly before daisy chaining them.

Here, I'll show you how to do it for one of them:

image.thumb.png.9324757e5bcb5729ef94bffd30371059.png

You can connect the Pmod_out port of the PmodAQS to the JE Pmod port on your Zybo Z7-20 by going to the Board tab, right-click on Connector JE and choose Connect Board Component....

image.png.032ba35d9684d7e24b434773efab643a.png

Make sure the Pmod_out port of the PmodAQS is selected/highlighted in blue and press OK.

image.png.d974353fc8e407aeb9a493f90ce70849.png

Doing it this way you won't have to mess around with the xdc constraints file.

Another way to do it is to right click the Pmod_out port and select Make External.

image.png.df495a208ccfd0214013bfcdfcf1d807.png

Now go ahead and create an HDL wrapper, open it and look for the following lines in the entity portion of the wrapper:

 image.png.dcf0d701e17860a2e23b74dc13875de9.png

These lines above are what you'll have to type into the xdc constraints file to make sure there will be a connection created between your board and your pmod port in which you'll connect the PmodAQS or whatever other Pmod.

In the xdc file uncomment the lines corresponding to the pmod port you want to use, in this case it's JE and replace whatever is between the "{}" squiggly braces with what you had in the HDL wrapper file. The result should look something like this:

image.png.f21e9ffcf0931e4c43defa996f13e387.png

 

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Thanks so much for your long explanation. May I ask can your one works for JC connection? I don't want to use JE. And I realise that JE and JC are different type of port. I am currently doing the vertical farming project and I want the JE to be used for relay to control the LED and water pump. Now, I may give up on IOXP and use the first layer of JC port for AQS connection and second layer of JC port for HYGRO connection. 

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Posted (edited)

image.thumb.png.3fbbdfc105c5b546600cd29da14098df.pngI am thinking if I can connect the specific pin in the port JC with specifc pin in the Pmod HYGRO or Pmod AQS?  Maybe from PmodOut. I am not so sure? 

 

Edited by lukelouyu
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