Oscilloscope output for 6.78 MHz frequency pulse

[Yogita]

I am using a Nexys-4 DDR board which has an internal clock of 100 MHz frequency. I am using clocking wizard to generate a pulse of 6.78 MHz and duty ratio of 0.3. I am getting the correct result in simulations but when I observe the output on oscilloscope I do not see a proper pulse. It does not have sharp edges. I get a proper output for lower frequencies. I am unable to find out what is the reason behind this. I am using a 200 MHz bandwidth DSO and an x10 probe for measuring the output.

Thanks,

Yogita

[Pavel]

I'd suggest checking the parameters of the pin that outputs this signal. I think that setting Slew Type to FAST and Drive Strength to 8 or 12 should help make the edges of pulses sharper.

In Vivado, the parameters of the pins are accessible via the I/O Ports window (RTL ANALYSIS -> Schematic -> Window -> I/O Ports).

[zygot]

8 hours ago, Yogita said:

do not see a proper pulse. It does not have sharp edges. I get a proper output for lower frequencies.

Welcome to the real world. If properly terminated your clock would appear to be much closer to your concept of an idealized signal. Set the constraint for your clock output to external termination and give it 16 mA of output drive. Then connect it to your scope though a 50 ohm coax cable. You need to terminate the cable at the scope input. This can usually be done through a setting in the scope. If not a tee connector and a 50 termination load will do the trick. (connecting your signal to the coax is the tricky part... don't damage your board )

Your question makes for a good project for a first year out-of-school engineer. What happened to my nice clock? I encourage you to do some research and find answers. You can also simulate the effects of a badly terminated or poorly matched transmission line on a signal using Spice or other analog simulator. This is a necessary part of an education for a would be FPGA developer. You can still find answers in the application notes of digital logic vendors though, sadly, not the old print references.

High frequency switching signals like those in digital design, and high voltage or high current switching like those the power company uses are subject to the effects of impedance, in particular the L and C parts. A digital logic simulator doesn't care about impedance.

Once you understand why your clock doesn't look like the simulator clocks you will be in a position to understand how to set output drive constraints effectively.

BTW, to me your signal looks pretty darn good for your test setup.

Bonus question. If you get a scope/probe setup with a much higher analog bandwidth and crank up the horizontal rate, the sides of the waveform aren't exactly vertical. Why is that?

One last thought. In order to use test equipment effectively, you have to understand how the render images that are intended to represent actual signals.

[edit] I've highlighted the keywords for your educational quest.

[edit] My suggestion about the 16 mA drive might be muddling my point. Since our receiver is a scope we don't care about the voltage span of the receiver... at least in the context of this discussion. Always try to use the minimum drive current appropriate for the load and receiver requirements.

[zygot]

On 3/15/2021 at 7:31 AM, Pavel said:

I think that setting Slew Type to FAST and Drive Strength to 8 or 12 should help make the edges of pulses sharper.

Not necessarily. In fact putting more energy into a badly designed transmission line with a badly matched load impedance is likely to make thing worse... a lot worse...

[last edit] I didn't intend to make another post to the thread since the person who asked the question has long since abandoned it. However, It's been made clear to me that at least one person incorrectly inferred that the following paragraph was a reference to him. I want to make it clear that it was intended to stand on it's own and is not a reference to anyone in particular. The last sentence that has a reference to Pavel was not in my original post but added later in an attempt to avoid confusion. Obviously, I did that poorly too. I apologize for the confusion that my admittedly poorly constructed post caused.

Again, I do like the idea of trying this out as a personal educational quest. If you know what you are doing, experimentation is fun and informative. On the other hand, if you don't understand the basic concepts it's easy to draw the wrong conclusions from experimental measurements and data. This is a basic principal of engineering and science. While not always satisfying, a scientific methodology is much preferable to mysticism, folklore, and outright disinformation campaigns ( all the rage these days unfortunately) ... at least for developing an understanding of the real world and how to get along with 'mother nature'.  I'm not suggesting that Pavel's advice is intentionally wrong, but as a general statement out of any particular context it certainly isn't correct either. I just want to avoid confusion on that point. [NOTE: Nothing in this paragraph is a reference to anyone but was meant as a caution to those engaged in personal educational quests... I've learned this from personal experience.

Bandwidth requirements are related to slew rates, not switching rates necessarily.

While were on the topic of bandwidth. A scope with a 200 MHz bandwidth sounds high. A 6 Mhz clock might seem low. While we know from Shannon that we need an Fs of at least 2X the signal of interest to get useful information this doesn't mean that the data that we obtain from minimal sampling can be used to produce an idealized picture of all of the details that we might want to see. Of course the complete answer is more complicated.

[Pavel]

Here is a link to an interesting comparison of signal edges for different connections between the signal source and the oscilloscope:

https://www.edn.com/sharpen-rising-and-falling-edges/

Even in the worst case the peak-to-peak rise time is less than 5 ns.

So, it should be possible to obtain sharper edges than shown in the original question even with a pretty generic probe.

I can obtain 5 ns peak-to-peak rise time on my 200 MHz oscilloscope without any effort.

However, I've just checked the schematics of the Nexys-4 board at this link and I see 200 Ohm resistors connected in series between the PMOD connectors and the FPGA pins. I think that these resistors are responsible for the slow peak-to-peak rise time shown in the original question.

[zygot]

1 hour ago, Pavel said:

I see 200 Ohm resistors connected in series between the PMOD connectors and the FPGA pins. I think that these resistors are responsible for the slow peak-to-peak rise time shown

I didn't even think about where the signal was being probed. You are correct about the PMOD pins all being connected to the FPGA pins through a series resistor. These certainly do have an effect on how a scope would show a signal probed at a PMOD pin. I don't know of a reason why series resistors would appreciably affect slew rate. I have observed a slow skew constraint for an Artix device resulting in rise and fall times in the 4-5 ns range. You can find switching specifications for Artix devices in the datasheet. If the picture above was probed on a PMOD pin the 200 ohm series resistor helps explain why the signal looks as good as it does. I believe that the 200 ohm series resistors are meant as protection devices more than anything. Series resistors are one form of termination for signal integrity. In general though they are 1/2 the driver output impedance and should be as close to the driver pin ( or ball ) as possible. For general purpose IO that can be either an input or an output this presents an obvious problem. Digilent rates their standard PMODs as supporting 10 MHz signals.

16 hours ago, Yogita said:

I am getting the correct result in simulations but when I observe the output on oscilloscope I do not see a proper pulse. It does not have sharp edges.

Perhaps, what I should have done in my first reply is ask @Yogitawhat specifically he sees on the scope rendering that is bothersome. I don't see ringing or overshoot at the edges. This is good. I suspect that the slight rounding at the edges is primarily due to limited bandwidth, both with the measurement setup and equipment and the signal traces on the PCB. You might not think that the 15 pF from the scope probe or the additional LC effects of vias and connector pins would have any effect on a signal but in aggregate they do. Couple this with a 200 ohm series resistor and you have a significant filter, and band-limited transmission line. Are you concerned about whether or not your clock will work on an external circuit?

I'm not sure that your scope/probe is adequate for formal testing but it would be easy to try different combinations of slew rate and current drive and see how it changes. The standard ground clip on most probes is too long for really accurate testing. Usually there are spring type ground clips which offer some improvement. It can be hard to separate the test equipment from the Device Under Test.. especially with an oscilloscope.

From previous comments that I've made here understand that FAST slew constraints require more transmission line bandwidth than SLOW skew constraints. More current drive requires a transmission line and terminating impedance that better matches the driver impedance or you will get ringing, and overshoot due to reflections wherever there is a mismatch. When you are designing a PCB with fixed external inputs and outputs you can do a pretty good job of this. When you have general purpose IO on PMOD style headers and the signals are the last to be laid out there's only so much that you can do with those IO pins.

[Pavel]

16 hours ago, zygot said:

I'm not suggesting that Pavel's advice is intentionally wrong, but as a general statement out of any particular context it certainly isn't correct either.

My recommendation was not a general statement and the context was very well defined: Nexys-4 DDR board, 200 MHz oscilloscope, x10 probe.

Here is a link to an application note explaining how drive strength affects the edges of the signal:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an476.pdf

Figure 3 on page 5 shows a pulse with three different drive strength settings. Here is a copy of this figure:

I think it shows clearly enough that increasing the drive strength can help make the edges of pulses sharper.

[zygot]

6 hours ago, Pavel said:

5 hours ago, Pavel said:

 

 

I think it shows clearly enough that increasing the drive strength can help make the edges of pulses sharper.

 

Pictures are nice but out of context they can be misleading. The application note that you reference deals with what the authors refer to as 'over-driving' and 'under-driving' loads. You should read the whole application note as it supports my notion that learning about proper termination and transmission line concepts is a good idea. What I see in the scope shot that was presented above doesn't look like 'under-driving' to me. Cherry-picking one picture from an application note to support your assertions and ignoring the rest of the content isn't very helpful to a discussion.

Don't stop with just one application note, though if you read it carefully there is good information to be absorbed in the one you refer to. It just isn't by any means a complete treatise on the subject. The concepts of proper digital design are broad. If you are going to connect external components to your FPGA device then learn how to do digital design. You can find good information from programmable logic vendor application notes and of course digital logic vendor reference material. I'm just suggesting that being more informed is better than being less informed if you don't understand why things don't appear to behave as you expect them to.

Trying to obtain 'sharp edges' isn't necessarily a good objective. I fact, getting 'less sharp edges' is the point of selecting a slow slew rate. Lot's of digital devices intentionally slow slew rates to obtain faster and more reliable data transmission. Of course edge rates can be too slow. The objective of digital design is to convey signals between nodes without generating harmful artifacts like EMI, ringing, overshoot, undershoot etc. Again, to anyone interesting in the subject I suggest embarking on a quest to take advantage of the material that exists to guide you through the basic concepts. This is a natural part of the skill set for most people wanting to use programmable logic as creating custom interfaces is what they excel at. and custom interfaces imply doing a bit of digital logic design.

As, the only people currently adding to this thread doesn't include the person asking for guidance I suggest that further discussion be done on a new post. I'm afraid that this discussion has veered away from the original post onto unrelated subject matter.

 

 

[Pavel]

I'm very surprised to see this kind of reaction to my initial answer and my additional comments.

Let me try to explain one more time why I think my initial answer is not wrong.

Here is the description of the setup from the original question:

• Nexys-4 DDR board
• 200 MHz oscilloscope
• x10 probe

The original question:

Quote

I am getting the correct result in simulations but when I observe the output on oscilloscope I do not see a proper pulse. It does not have sharp edges. I get a proper output for lower frequencies. I am unable to find out what is the reason behind this.

I think the problem is trivial and there is no need to introduce any additional complexities to model it. We basically have a capacitor (the oscilloscope probe and the oscilloscope input) periodically charged and discharged with a limited current (Drive Strength parameter) and with additional 200 Ohm resistance connected in series between the current limiter and the capacitor.

Here is how the shape of the edges shown in the original question can be reproduced with an RC circuit and a current limiter:

• current limited to 4 mA

• current limited to 8 mA

 

It can be  clearly seen that when the current limit increases, the rise time decreases. So, it's possible to make the edges of pulses sharper by increasing the value of the Drive Strength parameter.

Here are a few comments about the model:

• diodes D1 and D2 limit the current to model the Drive Strength parameter of the FPGA
• R1 models a 200 Ohm resistor connected in series between the PMOD connector and the FPGA pin
• C1 models the combined capacitance of the probe and of the oscilloscope input

[Ciprian]

On 3/16/2021 at 2:50 PM, zygot said:

I'm afraid that this discussion has veered away from the original post onto unrelated subject matter.

There seams to be a trend  off this, on this forum, when strong willed engineers express their Opinions. 

[xc6lx45]

Hi,

most likely your scope and probe are the bottleneck.
I remember doing the experiment once, and getting rise times around 3 ns from one of the direct outputs of a CMOD A7, after switching to an active probe on a "non-hobbyist" scope.