Using SPI0 on CPU0 and SPI1 on CPU1 zynq 7000

[fpga_123]

Hello,

 

I wish to use SPI0 on CPU0 and SPI1 on CPU1 in zynq 7000. I wish to have both the CPUs running FreeRTOS. I want SPI0 and SPI1 to communicate with each other in loopback mode. How do I do that?

Inside the block design in Vivado, Using PS IP, do I enable SPI0 and SPI1 with MIO/EMIO pins? What exactly needs to be done and then how do I proceed in Xilinx SDK?

I know that xap1079 that runs Bare Metal OS on both CPUs but how do I do that for FReeRTOS and make the SPIs talk to each other?

@JColvin

Thanks,

[JColvin]

Hi @fpga_123,

Digilent does not have much to offer in terms of FreeRTOS; you can see all of the FreeRTOS materials that we have at this link here: https://reference.digilentinc.com/doku.php?id=start&do=search&q=freertos. You'll note that the latest version of the Zynq based materials was for 2017.4 and I have not heard of plans to update this. The two links for the Arty are both for a Xilinx made project that just happens to use the Digilent made FPGA. This Forum thread (https://forum.digilentinc.com/topic/4292-running-xapp1079-on-zybo/) is what I am aware of for what Digilent has for XAPP1079.

Enabling SPI0 and SPI1 is more straightforward; you can simply double click into the Zynq IP in the Block Design, choose the MIO Configuration tab, and enable the SPI0 and SPI1 in the I/O Peripherals dropdown and choose for them to use MIO pins or EMIO. Note however MIO would provide the PS access to some dedicated external pins and EMIO lets you decide what external connections you might want to use. Neither really facilitates two cpu cores communicating between each other. You would instead want to use some sort of shared memory like it is described in XAPP1079.

 

Thanks,
JColvin