Question

Hi All,

I am working with a ZedBoard trying to test the output functionality of the Pmod headers. The Pmod headers on this ZedBoard have worked in the past, however, when I try to work with them now it appears that they do not transmit any output data. I've tried this for all four programmable logic accessible headers (JA1, JB1, JC1, JD1). When I assign the output to the LEDs I am able to see the output successfully, but it does not come through the Pmod headers.

Here is a very simple HDL file and constraints file that I'm using on my ZedBoard that should produce output on the Pmod headers.

 

HDL File (dut.v):

`timescale 1ns / 1ps

module dut(

    output PMOD

    );

    assign PMOD = 1;

endmodule

 

Constraints File Contents (constraints.xdc):

# ----------------------------------------------------------------------------

# JA Pmod - Bank 13

# ----------------------------------------------------------------------------

set_property PACKAGE_PIN Y11  [get_ports {PMOD}];  # "JA1"

set_property PACKAGE_PIN AA8  [get_ports {PMOD}];  # "JA10"

set_property PACKAGE_PIN AA11 [get_ports {PMOD}];  # "JA2"

set_property PACKAGE_PIN Y10  [get_ports {PMOD}];  # "JA3"

set_property PACKAGE_PIN AA9  [get_ports {PMOD}];  # "JA4"

set_property PACKAGE_PIN AB11 [get_ports {PMOD}];  # "JA7"

set_property PACKAGE_PIN AB10 [get_ports {PMOD}];  # "JA8"

set_property PACKAGE_PIN AB9  [get_ports {PMOD}];  # "JA9"

# ----------------------------------------------------------------------------

# JB Pmod - Bank 13

# ----------------------------------------------------------------------------

set_property PACKAGE_PIN W12 [get_ports {PMOD}];  # "JB1"

set_property PACKAGE_PIN W11 [get_ports {PMOD}];  # "JB2"

set_property PACKAGE_PIN V10 [get_ports {PMOD}];  # "JB3"

set_property PACKAGE_PIN W8 [get_ports {PMOD}];  # "JB4"

set_property PACKAGE_PIN V12 [get_ports {PMOD}];  # "JB7"

set_property PACKAGE_PIN W10 [get_ports {PMOD}];  # "JB8"

set_property PACKAGE_PIN V9 [get_ports {PMOD}];  # "JB9"

set_property PACKAGE_PIN V8 [get_ports {PMOD}];  # "JB10"

# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard.

set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];

 

Has anyone experienced this faulty behavior? Are they any workarounds or solutions?

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Has anyone experienced this faulty behavior?

That's some strange Verilog and constraints. Did you bother to read the synthesis and Implementation messages? I'm pretty sure that it's all you.

It might be better to use the switch inputs to set outputs on PMOD pins, assuming that create a design with outputs...

Start off with a review of Verilog syntax.

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