realt time outputs Generating outputs from the board from a file at a specific frequency

[Vinay EGK]

Hi,

I am super new to this. Trying to generate some outputs from the board by reading some files in the testbench at a particular frequency.

Any help or suggestions would be super helpful as I am trying to test a digital ASIC with the board and I am trying to replicate the testbench for the ASIC through the FPGA board Basys3.

Simply put, can my FPGA output some signals from my testbench using some files meant for another top module?

Regards

[zygot]

Your question is confusing me.

A testbench is code meant to be run in a simulator, not on hardware. Generally, testbench code uses aspects of an HDL that can't be synthesized.

It sounds to me like your task might be to create a hardware implementation that can be run on your Basys3 and replicate the general test vectors that the testbench generates. This implies that you have your ASIC on one board and a physical connection to the Basys3. Such a plan is not as trivial as it might seem, at least if you have specific tests to perform. The concept, if I'm understanding it correctly,  has potential problems. How are you going to verify the stimulus response? How are you going to know if the additional hardware has added to the complexity of verification? There are a lot of behaviors that can be overlooked with such a setup.

Perhaps another shot at an explanation would help.

[Vinay EGK]

I am so sorry. I am so not able to articulate this well.

I recently taped out an ASIC and am currently trying to test it. My idea is to generate the inputs to the ASIC the same as its RTL netlist testbench. I thought I could use an FPGA board to do the same, use the FPGA board as a buffer to generate real inputs to my chip.

In other words, I want my FPGA to read some input files and output them at frequency, lets say 256kHz, which will act as inputs to my ASIC.

I want to write the testbench for the FPGA such that it would read some files on a clock and send them as input to the FPGA and then the FPGA would produce the same inputs as outputs at a give frequency.

Read files in FPGA testbench ---> send to FPGA--->Output the FPGA inputs(fixed freq)--->use these FPGA outputs as inputs to my chip

Is this possible? I could give more explanation about this if you find the above explanation unclear.

Thanks for responding so soon.

[zygot]

40 minutes ago, Vinay EGK said:

Read files in FPGA testbench ---> send to FPGA--->Output the FPGA inputs(fixed freq)--->use these FPGA outputs as inputs to my chip

Well, then I did get the idea as you first stated it.

Can you imolement an application in your Basys3 that you can send the contents of a file to? Absolutely, yes. Can your Basys3 application convert this information into test vector signals that drive inputs to your ASIC? Well, that's not clear. I doubt it but I don't know what that file contents are. This isn't as straightforward or trivial as you might presume it to be. Would such a setup be a good way to verify the performance of your ASIC? I doubt it, but I don't know what the test-parameters and specifications are.

Simulation is excellent at some aspects of verification, even the best way for parts of verification. Connecting a Basys3 to your ASIC via wires has a very limited usefulness for verification and will most likely result in testing something other than what you think that you are testing.

A better way to test ans ASIC would be through boundary scan if the ASIC has that capability. This would also be of limited usefulness. There's a whole industry dedicated to producing such equipment that a Basys3 can't replace.

I don't think that you are understanding my comments about testbenches. Reading a stimulus file into a testbench for simulation is easy to do and standard industry practice. Reading a testbench and stimulating DUT inputs and analyzing DUT outputs is a very different matter.

It might just be that your testing requirements are not very comprehensive and my comments are irrelevant. I have very a explicit notion of what physical hardware testing should entail. 

[Vinay EGK]

18 minutes ago, zygot said:

Well, then I did get the idea as you first stated it.

Can you imolement an application in your Basys3 that you can send the contents of a file to? Absolutely, yes. Can your Basys3 application convert this information into test vector signals that drive inputs to your ASIC? Well, that's not clear. I doubt it but I don't know what that file contents are. This isn't as straightforward or trivial as you might presume it to be. Would such a setup be a good way to verify the performance of your ASIC? I doubt it, but I don't know what the test-parameters and specifications are.

Simulation is excellent at some aspects of verification, even the best way for parts of verification. Connecting a Basys3 to your ASIC via wires has a very limited usefulness for verification and will most likely result in testing something other than what you think that you are testing.

A better way to test ans ASIC would be through boundary scan if the ASIC has that capability. This would also be of limited usefulness. There's a whole industry dedicated to producing such equipment that a Basys3 can't replace.

I don't think that you are understanding my comments about testbenches. Reading a stimulus file into a testbench for simulation is easy to do and standard industry practice. Reading a testbench and stimulating DUT inputs and analyzing DUT outputs is a very different matter.

It might just be that your testing requirements are not very comprehensive and my comments are irrelevant. I have very a explicit notion of what physical hardware testing should entail. 

To clarify your comment about verifying the ASIC, I believe your perception is a bit different. To put it clearly,

1. The files contain a stream of serial binary inputs to the ASIC.
2. The intention of this test procedure of this ASIC is to verify its application and not its verification itself, the details for which I cannot put here.

Yes, as you were saying, we are trying to generate the test vectors for the ASIC using the FPGA.

On this note, if you could point to some ways to be able to just read a file and then produce the file contents as outputs from the Basys3 board would be appreciated a lot.
If you just take away the whole ASIC testing out of this, the question that would stand would perhaps be this:

Can I somehow generate binary outputs from the Basys3 board, the details for which would come from a file?

Thank you.

[zygot]

Yes, there would be a number of ways to create an application for the Basys3 that would produce signals, that is toggle output pins at a particular frequency in a particular pattern, on GPIO connector pins that could drive inputs to your ASIC. You could instantiate a UART in your Basys3 design so that en external program running on a PC could run a test based on the testbench contents. This would allow the same design to run an arbitrary test instead of only one. Python is a good language for serial control. I use a UART in most of my designs as both a user interface and for debugging. There are examples posted in the Digital Project Vault. Usually, sending test vectors into a DUT involves capturing output signals and determining if they are correct. Of course static analysis is different from AC switching analysis.

How you would implement such a design depends on your HDL skills and of course the details of the testing objectives.   But sure, you can do this using an FPGA platform.

You might find it easier to do without the FPGA though. A micro-controller could do the same thing in software. An FT232H Mini-Module connected through a USB port on your PC could do the same thing in JTAG or bit-bang mode, again as a software project. There are a lot of ways to generate a stream of binary data on a wire that mimic a script.