I am trying to use the Ethernet PHY on the Genesys2 card and I need to write the timing constraints for the Xilinx FPGA (the ones provided in the XDC file of the Ethernet IP do not match the PHY timing constraints)
The design configures the PHY in hardware (via strapping resistors) to add 2ns delay to the TXC line (4.7k pull up resistor on PHY pin RXD1) so that the FPGA sends out both clock and data at the same time (+/-0.5ns tolerance). The PHY will then add the 2ns delay to meet setup/hold.
On the receiver side (i.e. PHY out, FPGA In) the PHY is configured for no delay (4.7k pull down resistor on PHY pin LED2). Is the ETH_RX_CLK trace length longer than the RXD/RXCTL traces as suggested in the PHY datasheet (i.e. "This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5ns and less than 2.0ns will be added to the associated clock signal.") or are these traces matched?
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stcrana
Hello,
I am trying to use the Ethernet PHY on the Genesys2 card and I need to write the timing constraints for the Xilinx FPGA (the ones provided in the XDC file of the Ethernet IP do not match the PHY timing constraints)
The design configures the PHY in hardware (via strapping resistors) to add 2ns delay to the TXC line (4.7k pull up resistor on PHY pin RXD1) so that the FPGA sends out both clock and data at the same time (+/-0.5ns tolerance). The PHY will then add the 2ns delay to meet setup/hold.
On the receiver side (i.e. PHY out, FPGA In) the PHY is configured for no delay (4.7k pull down resistor on PHY pin LED2). Is the ETH_RX_CLK trace length longer than the RXD/RXCTL traces as suggested in the PHY datasheet (i.e. "This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5ns and less than 2.0ns will be added to the associated clock signal.") or are these traces matched?
PHY datasheet: https://www.semiconductorstore.com/pages/asp/DownloadDirect.asp?sid=1614664716277
See page 65 for mentioned quote.
Thank you
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