High speed serial link with FPGA

[falcon98]

Hi all,

 

I am developing a serial to parallel link for transmission of high speed digital pulses. Using UART logic on Spartan 3E boards , I am able to transfer 100 KHz pulses (8 channels) and recover them on receiver board. I am using DCM to provide 250 MHz clock to the logic.

I am targeting 10-50 MHz pulses (8Channels) transmission on FPGA boards. I have some spartan 6 boards with me which can support upto 1 GHz clock using BUFPLLs.

Can anyone provide a suggestion on how can I improve the speed of logic in order to achieve higher pulse frequency.

Should I user ISERDES/OSERDES...any tutorial on how to use these IOs on FPGA.

Pls suggest and let me know if I am no clear on any point.

Thanks

[zygot]

The UART is a an asynchronous interface. Your approach is correct. An 8X oversampling Fs should be sufficient, depending on how your HDL UART is designed.

You might find this project interesting: https://forum.digilentinc.com/topic/20479-inter-board-data-transfer-project/

You should be able to achieve at least 12 Mbaud with a well designed UART with logic clocked at 250 MHz.
There are many ways to limit the actual performance of any logic design operating on hardware. The most important is having good transmission lines between the driver and the receiver buffers. Impedance matching is critical. Another limiting factor is driver slew rate and current drive. At 250 MHz a slow skew output might have a rise or fall time exceeding your sampling period. A driver set for higher current drive will put a lot more energy into the transmission line, creating ovesrhoot. Selection of IOSTANDARD might be a factor.  [edit] I forgot to mention that the regular Digilent PMOD connector GPIO pins have seried 200 ohm resistors which complicate things. Digilent rates these PMODs for about 10 Mbps toggling rates though this might be conservative.  If you want to combine parallel bits to form a wider data bus then trace length matching becomes an issue to consider.

A problem with an asynchronous interface like the UART is that it's impossible to create timing constraints as there is no clock reference. The project that I mentioned worked at 40 Mbaud rates between two boards but at a higher Fs. You might consider using a USART, which is a synchronous cousin of the UART. With a source synchronous clock reference you can gain some control over the place and route tools by providing good timing constraints. Your interface will need an FPGA pins capable of driving the clocking infrastructure.

Designing an interface that only connect to one FPGA board is 'cheating'. To really test out your interface you will need 2 separate boards with unrelated clocks driving the logic, at least for asynchronous interfaces.

I don't remember if the Spartan 3 series supports IOSERDES but this would definitely help. So would clocking the IOB. Clocking for the IOSERDES is tricky. Xilinx has application notes on a variety of  related topics. At the cost of doubling the number of pins in your interface a differential IOSTANDARD like LVDS would ease the transmission line implementation. Lastly, there are self-clocking interfaces like bi-phase that encode a clock in the data transitions. Another project that might be of interest is this one: https://forum.digilentinc.com/topic/2898-differential-pmod-challenge/ 

 

[falcon98]

Hi ZYgot,

 

Thanks for your reply.

I suppose , I can transfer clock along with data to form USRT to get higher data rates. Is framing required in USRT?

In your suggested code I find that you are taking 4 bit input in the Transmitter and output is 8 bit wide. Is the project only for differential  outputs.

[zygot]

The project that I referred to takes advantage of the assumption that the differential pairs of the differential PMODs are reasonably well matched though not necessarily between pairs. That experiment suggests that the differential PMODs, at least on the platforms that I've tried it on don't use differential pcb trace layouts, which is good for this type of project. This particular UART sends 2 bits at a time instead of 1. The normal PMODs have series resistors and are rated by Digilent at around 10 MHz toggling rates.

If you go with a USART then you need at least one clock capable pin connected to the interface headers. The Genesys2 does, the Nexys Video doesn't. There are two big problems with the old 6 or 12 pin PMODs. One is that there aren't enough pins to work with for most general purpose interfaces. the other is that very few have clock capable pins assigned to them. I've long argued that it's well past time that Digilent do a refresh of their very limited and haphazard approach to PMODs but so far nothing's changed. I suspect that there's a poster on the wall of someone at Digilent listing things that will never happen and with my user name at the top...

[edit] BTW, not only would a USRT with a source synchronous reference clock be easier to design with but it allows for adding useful timing constraints which will make any implementation more robust at higher clock rates. The problem is having access to those pins that can be connected to the clocking infrastructure of the FPGA.

I've always said that it's better to select a platform for suitability for any particular project than buy a platform hoping that it will work.

Might I suggest that 2 DE0 Nano, each approximately the same cost as a CMOD, might be a better choice of hardware. I'd suggest the CMOD but it has a number of issues like exxternal memory and only 1 pin connected to GND ( except for the 2 on the PMOD.. but there's no good way to attach these to an add-on pcb. ).