Spliting single wires off of a bus in Vivado

[rt54321]

Greetings All!  I'm working through the basic tutorials on the AXI GPIO blocks, and interrupts, with the Arty Z7.

In the current design using axi_gpio_0, pressing any of the four pushbuttons does cause an interrupt in my code (great!).  Now, I want to move the gpio_0 input to another pin (say, A1 on the Arty Z7 board - I'm not using the XADC).

I see that the GPIO part of the gpio_0 block is a bus (a 4-wire bus in this case, that goes to 4 buttons).  Now, I only want to use 1 wire of gpio_0 to connect it to an output port (which will be A1 in the constraints file).  Do I use a slice IP block to do this?

[Niță Eduard]

Hello @rt54321,
From what I can tell, you implemented the button connection using the "Connect board component" option. This forces the AXI GPIO to be configured as "All inputs".
I would recommend disconnecting the AXI GPIO from the board sidebar, reconfiguring the AXI GPIO to allow both inputs & outputs and then making the port of the AXI GPIO external (and after that creating an .XDC and constraining your ports).
The XDC would look similar to this (Disclaimer: I have used a ZYBO Z7 to constrain the GPIO ports (which were named GPIO_0) to a led and 3 buttons, so you will have to modify it according to your board and desired ports)

set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { GPIO_0_tri_io[0] }]; #IO_L23P_T3_35 Sch=led[0]
set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { GPIO_0_tri_io[1] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { GPIO_0_tri_io[2] }]; #IO_L24N_T3_34 Sch=btn[1]
set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { GPIO_0_tri_io[3] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]

You can find the Arty Z7 xdc files here (for both -10 and -20, whichever one you need) https://github.com/Digilent/digilent-xdc

After generating the hardware platform, in SDK/Vitis you should configure the data direction for the GPIO
So, for example, if you configured wire 0 of the GPIO as an output, you would do something like this:
 

	XGpio_SetDataDirection(&device, GPIO_CHANNEL, 0b1110);

 

 

I have attached some photos of the steps described.
Also, regarding the manual constraint flow, you can find more information at https://reference.digilentinc.com/vivado/getting-started-with-ipi/v2019.2#create_a_simple_block_design (above step 4 you should find Sidebard: Make External - Manual Constraint Flow)

Best wishes,
Eduard

[rt54321]

Thank you for your help Eduard!

I have deleted the original "buttons" port, and I right-clicked on the AXI "GPIO"-->Make External.  The port I named as GPIO_0, and the AXI port is only 1 bit wide (see screenshot).

In my constrains file, I want to set this new pin to A1 of the schematic, so I have:

set_property -dict { PACKAGE_PIN Y12   IOSTANDARD LVCMOS33 } [get_ports { GPIO_0[0] }]; #IO_L20P_T3_13      Sch=CK_A1

 

When I try to generate the bitstream, I get the following error:

[Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: BiDi RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 1 sites. Term: GPIO_0_tri_io[0]

I'm not sure if this is a problem with my AXI block, or my constraint file.

 

[rt54321]

Aha!  I think I found my mistake - I need to click on "Make Exernal" on the "gpio_io_t[:]" port (this makes a black wire), NOT the GPIO port (this makes a blue wire).

Thank you again for your help Eduard!