Microblaze server project on the Genesys 2 board

[Bayartsogt]

I am trying Microblaze server project on the Genesys 2 board. I followed the instruction. However on the 4.2) step, clock connection "option" there was not /mig_7series_0/ui_clk(100MHz) instead, there is was only /mig_7series_0/ui_clk(225MHz). I selected this option. Eventually, in my project m_axi_sg_aclk pin is open in the "axi_ethernet_0_dma" component. When I Validate Design it shows the following error:

 [BD 41-758] The following clock pins are not connected to a valid clock source: 
/axi_ethernet_0_dma/m_axi_sg_aclk

[thinkthinkthink]

On 2/24/2021 at 7:16 AM, Bayartsogt said:

I am trying Microblaze server project on the Genesys 2 board. I followed the instruction. However on the 4.2) step, clock connection "option" there was not /mig_7series_0/ui_clk(100MHz) instead, there is was only /mig_7series_0/ui_clk(225MHz). I selected this option. Eventually, in my project m_axi_sg_aclk pin is open in the "axi_ethernet_0_dma" component. When I Validate Design it shows the following error:

 [BD 41-758] The following clock pins are not connected to a valid clock source: 
/axi_ethernet_0_dma/m_axi_sg_aclk

What version of Vivado have you tried this on ? Because on 2020.1 ui_clk is 100MHz by default. 

However you can try playing around with the MIG's internal settings to try and obtain an ui_clk of 100MHz.

Double click on the MIG and then keep pressing Next until you see this:

Make sure Clock Period is set to 2500 ps, this should be the default setting that can give you an ui_clk of 100MHz.