Basys3 board General Purpose IO connections to JB

[jstander 0]

Hi,

I am using a Block Design for a Basys3 board on Vivado 2020.2. Is there a way using the AXI GPIO IP from Xilinx to connect directly to the JB pins so that the Microblaze can toggle pins on the port?

I have a GPIO IP block down connected to pins named jb but they are not making it to my top level desin.

 

Thank you,

Jennifer

[JColvin 439]

Hi @jstander,

You should be able to do this by making the GPIO external and then manually assigning those pins in an .xdc file. This is explained in a bit more detail in one of our Vivado guides here: https://reference.digilentinc.com/reference/programmable-logic/guides/getting-started-with-ipi#add_gpio_peripherals_to_a_block_design, specifically in the second method in that section I linked.

Let me know if you have any questions.

Thanks,
JColvin

[jstander 0]

This is a very helpful link, 

I indeed ended up doing something very similar except when I made the port external, it did not automatically update the wrapper like I had expected and the pins did not show up after on the design through the normal process of validating. 

I ended up having to click Generate Block Design to force the new IO to show up and then manually add the jb pins to the wrapper. I am not sure what went wrong but feel uneasy about asking students to make these manual changes. 

Any thoughts?

[jstander 0]

Just curious, I had the students make their own ALS interface. It seems like it could be easily attached to an AXI port for reading. Is there a good tutorial on how to add your IP to a Block design that uses a Digilent board file? For instance it would be awesome if I could just assign it to the JB port as if it were a custom PMOD.

I was also looking for a good reference on how to add software drivers for custom IP blocks and a summary on how the BSP packaged is organized to make it easier to find important information. 

Thank you again,

Jennifer

[JColvin 439]

Hi @jstander,

6 hours ago, jstander said:

I indeed ended up doing something very similar except when I made the port external, it did not automatically update the wrapper like I had expected and the pins did not show up after on the design through the normal process of validating. 

I ended up having to click Generate Block Design to force the new IO to show up and then manually add the jb pins to the wrapper. I am not sure what went wrong but feel uneasy about asking students to make these manual changes

Hmm, I would have expected Vivado to automatically update the wrapper as well, presuming when you originally created the wrapper that you kept the default selection of Vivado auto-update and manage the wrapper. Though sometimes I end up choosing to delete the wrapper, update a design, re-validate, then re-add the wrapper to make sure Vivado knew to incorporate the changes. I agree that having students make these manual changes is not ideal.

7 hours ago, jstander said:

I was also looking for a good reference on how to add software drivers for custom IP blocks and a summary on how the BSP packaged is organized to make it easier to find important information.

Digilent doesn't have any direct references on adding software drivers for custom IP blocks. I know Xilinx has extensive (albeit dense, but that's a byproduct of extensive) documentation on Vitis and BSP materials here and here.

I believe Digilent has some material on creating Pmod IPs themselves, though I've been told that this material is very old (references 2015.4 Xilinx material) and is not very "presentable" at least with regards to how other Digilent material is provided on our Wiki/reference site. I'm not even sure if the material would conform or not with the way our board files are currently set up (as evidenced by how the Pmod IP tcl scripts are not playing nicely with the newer versions of Vivado). If this does not deter you, I can see about getting this material to you.

Thanks,
JColvin