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MIO to FPGA pins


Question

I have been looking at the Zybo and Zed boards and I am trying to understand how the MIO pins get connected to the external pins. Where can I find a document that tells mw how and when the MIO pins are connected to external pins. Are they wired or they get programmed when a project that uses the PS is created.  

Any information is greatly appreciated.

Thanks,

Cherif

 

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The normal way that PS hardware like UARTs, Ethernet MACs, etc. get connected to PL connected pins is when you create a block design and plop a ZYNQ-7 into the design. For ZYNQ based boards this is the first step. If you double click on that block in your design it will allow you to set up the PS, including emio pin muxing.

I really encourage you to do a bit of homework reading relevant ZYNQ references provided by Xilinx. You should consider searching for a few tutorials about how the ZYNQ works and creating a project. There are tutorials about how to do exactly what your question suggests that will, at least, give you an idea of what's involved.

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