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larijan_ask@yahoo.com

Product 400 Mhz Clock In Atlys Board

Question

hi my working is on atlys board (spartan 6)i want to create a clock with 400 MHz frequency , when i use the ip-core(clocking - clocking Wizard 3.6) the error will be displayed . How i can write this code manualy ?  

the error is:

post-340-0-03219200-1420892981_thumb.png

 

thanks

Edited by Josh
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Hi Larijan_ask,

 

Yes, yes you can write the code manually - it is a lot quicker than using CoreGen IMO, And here is an example for you - 100MHz in, 400MHz out:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
 
entity clocking is
    Port ( clk100 : in  STD_LOGIC;
           clk400 : out  STD_LOGIC);
end clocking;
 
architecture Behavioral of clocking is
   signal clk100_buffered : STD_LOGIC;
   signal clk400_unbuffered : STD_LOGIC;
begin
 
 
buffer_input : BUFG
   port map (
      O => clk100_buffered, 
      I => clk100  
   );
 
 
DCM_CLKGEN_inst : DCM_CLKGEN
   generic map (
      CLKFXDV_DIVIDE  => 2,      -- CLKFXDV divide value (2, 4, 8, 16, 32)
      CLKFX_DIVIDE    => 2,      -- Divide value - D - (1-256)
      CLKFX_MD_MAX    => 4.0,    -- Specify maximum M/D ratio for timing anlysis
      CLKFX_MULTIPLY  => 8,      -- Multiply value - M - (2-256)
      CLKIN_PERIOD    => 10.0,   -- Input clock period specified in nS
      SPREAD_SPECTRUM => "NONE", -- Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD",
                                 -- "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2" 
      STARTUP_WAIT => FALSE      -- Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
   )
   port map (
      CLKFX     => clk400_unbuffered, -- 1-bit output: Generated clock output
      CLKFX180  => open,              -- 1-bit output: Generated clock output 180 degree out of phase from CLKFX.
      CLKFXDV   => open,              -- 1-bit output: Divided clock output
      LOCKED    => open,              -- 1-bit output: Locked output
      PROGDONE  => open,              -- 1-bit output: Active high output to indicate the successful re-programming
      STATUS    => open,              -- 2-bit output: DCM_CLKGEN status
      CLKIN     => clk100_buffered,   -- 1-bit input: Input clock
      FREEZEDCM => '0',               -- 1-bit input: Prevents frequency adjustments to input clock
      PROGCLK   => '0',               -- 1-bit input: Clock input for M/D reconfiguration
      PROGDATA  => '0',               -- 1-bit input: Serial data input for M/D reconfiguration
      PROGEN    => '0',               -- 1-bit input: Active high program enable
      RST       => '0'                -- 1-bit input: Reset input pin
   );
 
buffer_output : BUFG
   port map (
      O => clk400, 
      I => clk400_unbuffered  
   );
end Behavioral;

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