SPI mode 0 in WaveForms SDK: what is the value of the MOSI signal during a falling edge of SCLK?

[Nico G]

If I configure the SPI with mode 0 (polarity=0 and phase=0) and LSB in WaveForms SDK in the Digital Discovery or Analog Discovery 2, and I send the byte 163=0xA3=b10100011;
I would see the following:

Is it guaranteed that when there is a falling edge of SCLK, the MOSI takes the value just before the transition (the SCLK edge)?
What I mean is; is the following image accurate:

[maxwellfire]

The data pins must not change near where the clock has its sampling edge.

For a mode 0 SPI setup, the data is sampled on the rising edge, not the falling edge. The data changes near the falling edge.

Therefore your drawing is a bit misleading. MOSI isn't sampled just before a falling transition. It's sample a full half a clock pulse earlier. If MOSI is changing when the clock is also rising, the behavior is not well defined.

Here's a diagram.

Notice how IO is shown as changing somewhere in the middle between rising clock edges.

Here's another diagram:

t_DS is the time before the clock edge that the data signal must have settled. t_DH is the time that the data signal must remain constant after the clock edge before the data signal is allowed to change. These are known as the setup and hold time respectively.

This diagram also shows when the other device is going to send data. For mode 0, this happens on the falling edge of the clock after a delay of TD0 like you drew in your second diagram.

I hope this helped!

[attila]

Hi @Nico G

You can use the Logic Analyzer with Protocol to inspect the signal timings.