ethernet access to spartan 6 lx 45 board

[Gopal Krishna 0]

How to interface ethernet port of spartan 6 Lx45 FPGA board with LAN wire?

[zygot 226]

It would help if you specified the FPGA board that you are using.

[Gopal Krishna 0]

18 hours ago, zygot said:

It would help if you specified the FPGA board that you are using.

@zygot It is Atlys FPGA board.

[zygot 226]

The ATLYS has a GMII Ethernet PHY capable of 1 GbE data rates. This is the easiest of the PHY interfaces; even so it's not for beginners.

If you've never attempted an Ethernet PHY design one possibility is to do a MicroBlaze design with Ethernet and see what HDL code the Xilinx IP produces. The MAC will be encrypted but you can slog through the PHY interface. There are other Ethernet PHY interface designs for ISE out there on the internet to be found that will provide clues as to what your design will need.

For incoming data you will use the Rx clock out of the PHY. For outgoing data you will have to provide a suitable Tx clock, generally a forwarded 125 MHz 90 phase shifted relative to the logic in your design. Designs using Ethernet have at least 2 clock domains and usually at least 3 so you need to understand how to pass signals and data between clock domains properly.

You don't need a MAC to make use of the Ethernet PHY but you do need to understand the basics of Ethernet. It's a packet based protocol and all packets start of with the same synchronizing data.

I strongly suggest that no one try and connect their FPGA board to the internet.

That should be enough clues to get you started.