• 0

Configuring specific SPI communication in WaveForms SDK


Go to solution Solved by attila,

Question

I have a device that has a single 16-bits SPI shift register (for both transmissions and receptions). It responds to falling edges of SCLK. The input of the shift register is connected to MOSI and the output to MISO, as the following figure.

 

SPI.jpg

 

As the MOSI signal is input to the first flip-flop of the shift register, it should remain stable (not change) during a falling edge of SCLK, while MISO changes its value during a falling edge of SCLK. This way, MISO and MOSI signals are not synchronized.

I want to communicate with this device using WaveForms SDK. Is there a way to configure the SPI communication correctly?
With this I mean: is there a way of generating the SCLK and MOSI signals as shown in the figure above, and sample the MISO data in each rising edge of the SCLK?
I suspect functions FDwfDigitalSpiRead16 and FDwfDigitalSpiWrite16 assume MISO and MOSI signals are synchronized; so no SPI polarity and phase configuration would work correctly.

Edited by Nicolas Gammarano
Add more information
Link to post
Share on other sites

10 answers to this question

Recommended Posts

  • 0

Hi @Nico G

In SPI communication the active (data update) and sampling edges should be different.

Your device samples at falling edge so you should send data to it with active rising edge mode 1 (or 2)
https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Clock_polarity_and_phase

Your device updates the MISO on the sampling (falling) edge so the received data by the master will likely be corrupt.

Edited by attila
Link to post
Share on other sites
  • 0

@attila Thank you for your reply.

2 hours ago, attila said:

Hi @Nico G

In SPI communication the active (data update) and sampling edges should be different.

Your device samples at falling edge so you should send data to it with active rising edge mode 1 (or 2)
https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Clock_polarity_and_phase

Your device updates the MISO on the sampling (falling) edge so the received data by the master will likely be corrupt.

Is there a way or configuration to both transmit and receive correctly in this scenario (avoiding the received data by the master to be corrupt)?

Is there a way to configure

  • SPI mode 1 to generate the MOSI; but
  • SPI mode 0 to read the MISO?

Is there a way to solve this?

 

Thank you!

 

Link to post
Share on other sites
  • 0

Thank you @attila!

On 2/19/2021 at 7:20 AM, attila said:

Hi @Nico G

In the latest beta I've added a mode flag bit 2 (3rd) which changes the MISO sampling to be on the opposite edge of normal SPI mode.
https://forum.digilentinc.com/topic/8908-waveforms-beta-download/
With dwf.FDwfDigitalSpiModeSet(hdwf, c_int(5)) the MOSI is updated and MISO sampled at CLK rising edge.

 

Which version is this WaveForms beta that has this 3rd bit SPI mode flag? Where can I download it?

 

EDIT: I found the link here: 

However, I think the link to WaveForms beta v3.16.10 is incorrect.
It is http://s3//digilent/Software/Waveforms3Beta/3.16.10/digilent.waveforms_beta_v3.16.10_64bit.exe?_ga=2.222329307.1959141895.1613733661-1375308676.1613733661
but it should be https://digilent.s3-us-west-2.amazonaws.com/Software/Waveforms3Beta/3.16.10/digilent.waveforms_beta_v3.16.10_64bit.exe?_ga=2.222329307.1959141895.1613733661-1375308676.1613733661

One more question though. That WaveForms executable is for Windows 64-bit, is there a .deb for 64-bit Linux?

Edited by Nico G
Found the link
Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now