Genesys2 Problem DDR3 SDRAM

[stefano134]

Hi,
i am in possession of a digilent genesys 2 board and i am experiencing a big problem on the use of DDR3 SDRAM memory and ethernet port in vivado 2019.2. 
every time i try to insert in the block diagram the DDR3 SDRAM memory and the ethernet port, even if i can generate the bitstream without errors or critical warnings taking it to vitis and programming the board (even with a simple hello word program to print on the uart port) it doesn't work and doesn't give any sign of working. if i remove the ethernet or the sdram ddr3 everything works. i've been trying for a month and i have no results. i would like to know if there is a way to solve the problem or maybe i have a problem with the board and i have to replace it. i attach the images of the block design.

 

[zygot]

4 hours ago, stefano134 said:

if i remove the ethernet or the sdram ddr3 everything works.

Well that doesn't sound like a problem with your board. It does sound like a problem providing proper timing constraints and resulting in a poor place and route implementation. The Kintex device on the Genesys2 is more than capable of doing both interfaces simultaneously. What kind of timing scores are you getting?

[stefano134]

here are the times of the board
i see that it has a problem in the delays.
i tried of course to follow the tutorial of the board but it's not possible to follow them, since with the new files of the board they changed the ui_clk, and even changing the ui_clk the problems remain.
by now i've tried more than 30 different configurations and none of them works. is it possible that it's so complicated to make a simple block diagram with a DDR3 memory and an ethernet port? it would be enough for me just one working configuration.

[zygot]

5 hours ago, stefano134 said:

by now i've tried more than 30 different configurations and none of them works. is it possible that it's so complicated to make a simple block diagram with a DDR3 memory and an ethernet port?

The block diagram makes everything look simple doesn't it? Both the DDR and Ethernet RMII interfaces are non-trivial and require good timing constraints to help the synthesis and place and rout tools make good decisions about where to put the logic in order to meet timing. I don't use MicroBlaze or the block design flows so I can't really help you with that.  Digilent seems to have a User Demo for the Nexys Video board using the DDR and Ethernet but nothing similar for the Genesys2. Their support for the Genesys2 has always been worse than other boards. I don't think they've ever provided a demo that is comprehensive as far as all of the external components and connectors are concerned.

Throwing combinations at the wall is just going to tire you out. You need to learn how to figure out what the problem(s) is (are) and address them all.

One way to get really poor implementation results is to make the tools try and analyze timing for a lot of nets associated with different clock domains. You might try looking at the inter-clock timing. Using a signal created by one clock domain and used as an input to logic in another unrelated clock domain is a pretty reliable way to get the tools working onb solving the wrong problems... resulting in excessive delay paths.

Xilinx has a nice user guide for timing closure.

Unfortunately, the block design flow gives the impression that the tools are going to figure out all of the design requirements and do all of the hard work for you. Sometimes this works out OK. When it doesn't unwinding the design from the script generated design sources becomes very difficult, and in the case of parts of the Ethernet impossible as the source is encrypted. That's the price of convenience and trying to implement something that you don't fully understand.

You can look at the implementation logic placement to get a feel for where logic is relative to the IO pins, but this is complicated with the MicroBlaze stuck in the middle. You can also hunt down all of the constraint files to see what timing constraints, if any, the board design generation process gave you.

If you are going to do serious FPGA designs do you really want to rely on a third party who says "Hey just put my soft-processor in your design and drag and drop more IP into a schematic and I'll do everything for you", and then when you get a non-functional result is nowhere to be found? Are you expecting your FPGA board vendor to come to your rescue with answers?  Perhaps you'll get lucky but that's not likely especially if they don't provide good support for your board that works with your versio of the tools.

Edited February 5, 2021 by zygot

[stefano134]

I thought it wasn't that complex since looking at the Genesys 2 board tutorial :https://reference.digilentinc.com/learn/programmable-logic/tutorials/genesys-2-getting-started-with-microblaze-servers/start 
they follow the same steps as I do. 

[zygot]

I didn't notice that tutorial. A lot has changed between Vivado 2015 and Vivado 2019.2. But you point is well taken. It might not be totally unexpected to run into snags trying to upgrade a project from one version of Vivado to another but expecting a tutorial where you build a hardware project from scratch to work, regardless of the tools version, seems to be pretty reasonable.

It's possible that the original tutorial had things missing. You could try installing the same version of the tools as the tutorial used and see if that makes any difference. You might find that Vivado 2015 is a better tools version for some of your projects depending on what IP you want to use. Notice that the Ethernet functionality requires a temporary evaluation license so your hard work won't last long anyway.

Your experience is one reason why I don't use MicroBlaze or the board design flow, or even Xilinx IP in general.  Another reason is that when things aren't going well trying to debug it or closing timing is a lot easier when I have HDL source code that I understand.

I really like the Genesys2. If it had 2 standard SYZYGY and 1  SYZYGY transceiver ports instead of the PMOD connectors it'd be almost perfect as a general purpose FPGA platform. Because it has a faster speed grade device and the more capable Kintex device I've found that prototyping ideas is a lot easier than with the normal Artix boards. That is I can try out concepts without worrying too much about timing closure... except for DDR and Ethernet PHY interfaces.

[stefano134]

I finally managed to solve it, I had to manually move the registers of the axi ethernet block.
anyway i also tried to use their version of vivado, but the card files they use are not found.
anyway i thank you for your availability

[Danellee]

The Genesys 2 provides two interface types that can be used to transfer user data between a PC and an FPGA design. Specifically, it can be programmed from various sources, like USB thumb drive, microSD, the on-board non-volatile Flash or the on-board USB-JTAG programmer circuit.

It is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE toolset. Included in the box is a voucher that unlocks the Design Edition of Vivado that is device-locked to the Genesys 2. This allows designs to be implemented straight out of the box at no additional cost. The Design Edition of Vivado also unlocks the Logic Analyzer tool and still includes the ability to create Microblaze soft-core processor projects.