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hello, i'm trying to simulate the mig controller to test calibration>write>read operation. i'm using MT41J128M16xx-125 memory and ZYBO-020 board.

in simulation calibration is complete at 104us (nit_calib_complete =1) but and not able to receive the input data (app_wdf_data[127:0]) at the output pin (app_rd_data[127:0])

i check the vivado design example, in that also output data is random (as per me).

so anyone please help me with this 

what've i done so far:-

instantiate the mig_7series_0 in a top module

copy the  sim_tb_top (test bench in example design) and instantiate the top module with all files like u_delay and ddr3_module.

that's it. very basic (now in simulation console i gave all the inputs and checking for the output after calibration, but i'm not able to receive the correct output.

thank you.

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8 hours ago, lukum said:

hello, i'm trying to simulate the mig controller to test calibration>write>read operation. i'm using MT41J128M16xx-125 memory and ZYBO-020 board.

I'm a bit confused as to exactly what you are trying to do. The ZYBO doesn't have DDR connected to the PL. It does have DDR connected to the PS. I've never tried to simulate PS operation with external components... indeed I don't believe that this is possible, but I could be wrong. I really doubt that I'm wrong but would be happy to hear from someone who might know something that I don't.

If all you want to do is simulate a Mig example project perhaps you want to select a different board..??? Typically, these types of interface IP example projects have its own traffic data generator/checker.

Edited by zygot
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hii @zygot thanks for reply

yes, you are right about the zybo board, but i'm only looking for simulation, in simulation part i'm able to do calibration but after that MY OUTPUT data is shifted

why it is shifted that's my question. (screenshot7)

as per me it is some clock/time issue, cause memory might get different value at different time (what's that time? i don't know)

my mig works at 400Mhz and ddr3 at 800Mhz with data bit width of the user side 16*2*4==128 bits.

and one more this for this i need to keep hi_pri signal high, otherwise my app_rd_data give some values (random* that are used in calibration or in mig test side), why this so happing?

after 104us when calibration signal goes high, why app_rd_data gets values? (screenshot5).

 

 

Screenshot (7).png

Screenshot (5).png

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Ok, so you only want to do simulation and your references to the ZYBO are irrelevant.

So, what happens when your simulation isn't producing the expected output? Well, the answer is that you learn how to use the simulator to understand whats going on. The first place to start is with the external memory core. Read the reference material. Start reading through the source code. Fortunately, encrypted sources aren't a problem for the Mig IP. You should also understand how the simulation testbench works. You have the code. As you start figuring out what's going on you can add signals from modules deeper within the hierarchy to visualize signal interactions.

I really can't see the point of simulating a generic Mig design example except as a learning experience. So... pull  up your drawers and start learning already... You have questions. See if you can figure out how to find answers; that's what the simulator is for. If you ask better, more informed questions you are likely to get better help with your learning experience. Logic simulation isn't just about figuring out what the RTL is doing. It's also, perhaps more importantly, about training your brain to do competent and effective debugging, which means gaining an understanding of the nuanced and not so obvious details that a robust design requires.

 

Edited by zygot
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