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FPGA/AXI Audio with ZYNQ and PmodI2S2


Question

I am new to this so I am just guessing how to out stuff together.

I want to use the PmodI2S2 for Stereo Audio Input and Output.

I am using a Cora z7 with a ZYNQ.

I want to try and make two things:

A. Connect the PmodI2S2 via Axi and then write a software application in Vitis to send and receive audio data.

B. Connect the Pmod12S2 to logic and modify audio data. Possibly make an oscillator.

The "Pmod I2S2 FPGA Volume Control Demo" in the resources centre says it uses an AXI streaming interface.

So for part A. I made a new IP with an AXI streaming interface (just one way for line out) and a Pmod output that wraps some of the example code (removing the loop back bit). Then I connected it to DMA. and the DMA to the zynq. Not sure if this makes sense to do..

design_2.pdf

But then I am not sure how I get the address in vitis. do I just use the dma address ? I can't work out how it is all translated/mapped.

1811632779_Screenshotfrom2021-01-2416-46-16.thumb.png.f193c424c8e478b48f42596d26457ed3.png

Or.... should I be using a FIFO/ buffer in hardware and writing larger amount of data at a time ?? Is AXI streaming correct should I use something else ?

When I create new IP I have the choice:  Lite/Full/Stream but when I edit the IP in the packager and add interfaces the AXI interfaces have the following:

1175213014_Screenshotfrom2021-01-2416-42-49.png.18c7c59b95ead94e58b787f7a8cd7711.png

What is what in here ??

For Part B

The example loopback code uses the AXI streaming interface, but what should I use in logic or what would be a normal design for moving audio samples around in fpga ??

 

Any help

 

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Hi @jungle

AXI lite and full are memory-mapped interfaces, while the AXI stream interface is not. As such, you won't find the streams in the address editor. DMA is a good way to connect an AXI stream to one of these memory mapped interfaces. To send data to this stream, you should then be using the xaxidma drivers to set up and trigger the transfer. The DMA IP acts as an intermediary: for simple transfers, the processor hands it an address and a transaction length, and it reads each word of data out of that region of RAM, and sends it down the AXI stream.

Can also note that the DMA IP contains block RAM buffers.

There are some DMA audio demos for other boards (like for the Zybo Z7) that take this approach, and that should be useful for reference. There's an AXIS IP that handles I2S data in and out that can be found in that demo as well.

Thanks,

Arthur

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@jungle Can you please share how you got this working
I'm stuck at the interconnection of I2S receiver with Zynq PS.

I used a couple of IPs the FiFo width converter etc. but the problem is with number of bytes.

I2S sends 32 bytes but the DMA controller can handle 1.

Please guide me here I'm a bit stuck.

Regards, 

@artvvbAny help is appreciated.

 

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Hi @Sheraz

Mainly, one, make sure that your packets can fit in the DMA buffer, as set in hardware by the AXI DMA's buffer length register width parameter. Two, make sure that the number of bytes specified by the third argument of the XAxiDma_SimpleTransfer calls matches the actual length of your packets in bytes (not transfer beats).

If tlast doesn't show up on the transfer beat that the DMA is expecting (based on that third argument), then the IP can lock up.

How is your AXI DMA configured?

Thanks,

Arthur

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