Factory bitstreams for Nexys 4 and Nexys 4 DDR boards

[Arnaldo Oliveira]

Dear Sir or Madam,

 

Is it possible to provide the default/factory bitstreams for both Nexys 4 and Nexys 4 DDR boards?

Sometimes students need to reprogram the board’s FLASH, but it is useful to restore the factory configuration.

Thank you for your attention.

 

Best regards

Arnaldo Oliveira

[JColvin]

Hi @Arnaldo Oliveira,

The out of box demos for the various Nexys boards are available on the GitHub pages (Nexys 4, Nexys 4 DDR, Nexys A7). The release versions of the various projects were made in specific versions of Vivado so if you use the released project in a different version of Vivado you may need to regenerate the project. The release projects already contain the bitstream though which can be loaded from any version of Vivado.

If you want to reprogram the flash though with a .bin file, that will need to be separately generated.

Let me know if you have any questions.

Thanks,
JColvin

[charlycop]

On 1/22/2021 at 8:06 PM, JColvin said:

If you want to reprogram the flash though with a .bin file, that will need to be separately generated.

Let me know if you have any questions.

Hi @JColvin,

I did everything you said, and yes I can upload the .bit file provided, it's working.

But what I want is to reprogram the flash with the .BIN File. I checked the box in Vivado to generate the .bin file after regenerate the design. However I'm stuck in this step for ever (see attached screenshot)

Is there a way to get the .BIN file somewhere ?

Thanks,

Charly.

Dev board card I'm using : NEXYS 4 DDR
OS : Windows 10 pro
Vivado version : 2018.2 (like the project provided by Digilent on the github)

[JColvin]

Hi @charlycop,

I'm not able to comment too much on your system seemingly being stuck on the Generate IP 'ddr' portion. I know it can take awhile for synthesis and implementation to complete, especially on computers with lower speed processor cores, but I was at least able to download the file from the same Github link you provided onto my Windows 10 machine and generate the .bit and .bin file on Vivado 2018.2 for the Nexys 4 DDR.

Regardless, I have attached the two files that I generated for the OOB design; you'll need to press the red "PROG" button after loading the flash memory onto the device to have it start running on the board.

Thanks,
JColvin

Nexys4DdrUserDemo.bin Nexys4DdrUserDemo.bit

[charlycop]

1 hour ago, JColvin said:

Hi @charlycop,

I'm not able to comment too much on your system seemingly being stuck on the Generate IP 'ddr' portion. I know it can take awhile for synthesis and implementation to complete, especially on computers with lower speed processor cores, but I was at least able to download the file from the same Github link you provided onto my Windows 10 machine and generate the .bit and .bin file on Vivado 2018.2 for the Nexys 4 DDR.

Regardless, I have attached the two files that I generated for the OOB design; you'll need to press the red "PROG" button after loading the flash memory onto the device to have it start running on the board.

Thanks,
JColvin

Nexys4DdrUserDemo.bin 2.19 MB · 0 downloads Nexys4DdrUserDemo.bit 2.19 MB · 0 downloads

Thanks, it worked :)

I let it run for hours, and the synthesis was still not running, and the CPU activity completely quiet... and it's not new to me, I remember in university, I had the same problem, with my computer and many other computers...