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Can I configure CMODS6 I/O's for 1.2V LVCMOS?


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15 hours ago, [email protected] said:

The voltage for a given bank will always be constant, and controlled by the power provided for that bank.

Well, yes.. and not quite.

FPGA boards with FMC connectors like the Nexys Video and Genesys2 power some IO banks with Vadj. As the name suggests, this is a power supply with user select-able Vccio bank voltages. That doesn't mean that you can always run an IO bank at one voltage and change it later to something else during operation. Your input and output buffers have to be compatible with the IOSTANDARD that your FPGA pins are set to, and this is set before your bitstream is created. It is conceivable that one could do a partial reconfiguration and change functionality and IOBUF selection without powering down but it's not something that a normal application would require. You wouldn't want to do it unless required to do so. The selection of IOSTANDARD is constrained by the physical voltage powering the FPGA device IO banks, and possibly other factors like PCB trace routing and termination.

Assigning IOSTANDARD constraints to pins for a particular board is not a triviality. Unless you know what you are doing stay with the master constraints assignments, if these are provided as they are appropriate for whatever is connected externally to these pins. For pins routed to general purpose connectors you can change IOSTANDARD to something compatible with the Vccio powering IO bank associated with a particular pin. You figure out what the IO bank and Vccio is from the FPGA board schematics.

Be aware that pins associated with general purpose connectors are on IO banks with pins connected to fixed external components. This means that general purpose connectors aren't universal purpose connectors for most FPGA boards. One exception is FPGA boards that support the SYZYGY standard. Unlike the venerable PMOD this standard is designed to provide the most versatility in terms of IOSTANDARD and pins connected to them are always powered by Vadj. Better yet, every SYZYGY port connector can have it's own Vadj voltage independent of other SYZYGY ports. Pretty cool isn't it? You don't need a standard to design an FPGA board with SYZYGY-like performance; you just have to want to.... 

Be careful with Vadj. if your board has this.

Edited by zygot
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18 hours ago, [email protected] said:

Does Digilent offer any FPGA modules capable of LVCMOS 1.2V IO's?

As the semiconductor process feature size shrinks so does the voltages that the chips can tolerate. The UltraScale and UltraScale+ devices have IO banks that can be powered with 1.2V. In fact this is at the high end of their Vccio range. This also makes FMC mezzanine cards that were compatible with other older Xilinx devices not compatible with these devices.

If you really want need connect your Spartan 6 CMOD to 1.2V single-ended external logic you can use a dual power supply level translator buffer between the external pins and the FPGA pins. You can't select LVDS as an IOSTANDARD because your CMOD doesn't let you power any IO banks with a user provided power supply. You can design your own interface that converts 3.3V single-ended logic to an appropriate differential logic, and visa versa. At least you can if you know how to do digital design. It's a good bet, based on your question, that you don't.

Digilent makes one UltraScale ZYNQ board and sells at least one other from a 3rd party. There are a few SYZYGY compatible FPGA boards out there and Digilent sells a couple of them. The user is burdened with the responsibility of making sure that a particular FPGA board can supply Vadj = 1.2V or any other required Vccio voltage.

Edited by zygot
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