VHDL simulation of Accelerometer Tester


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Hi,

I'd like to mention that I completed a first-draft of a VHDL test-bench / verification environment, for the Accelerometer Tester design previously announced. The VHDL test-bench is capable of executing with the free GHDL simulator on Linux or on Windows Subsystem for Linux. (The MSYS2 version of GHDL on Windows appears to crash.) Take a look. I created the beginning of models for the Pmod SSD (7SD), Pmod CLS, Pmod ACL2--according to my usage of them in my project.

https://timothystotts.github.io/2021/01/08/vhdl-verification-of-fpga-serial-acl-tester-1-with-open-source-tools.html

Regards,

Tim S.

 

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