Wiring diagram for safely controlling 12V DC on Pmod OD1

[eyz]

Does anyone have a schematic showing safe wiring for controlling a 12V DC load with the Pmod OD1? I see in the reference manual there is a mention of the external power needing to be no higher than 5.25 volts, so I want to make sure I understand exactly what the requirements are.

From the reference manual at https://reference.digilentinc.com/reference/pmod/pmodod1/reference-manual -

"Any external power applied to the Pmod OD1 must be within 2.7V and 5.25V; however, it is recommended that Pmod is operated at 3.3V."

[JColvin]

Hi @eyz,

I apologize for the delay.

That line is in there for the IC1 and IC2 (the two schmitt triggers, https://www.onsemi.com/pub/Collateral/NL27WZ17-D.PDF, located prior to the N-FETs), as these ICs can only handle up to 5.5V from the host boards. If you leave JP1 disconnected (disconnecting the external power supply that can be applied to the separate J4 screw terminal from pin 6 on the 6-pin header), you can provide a 12V power supply and not hurt your board that way. I see that the reference manual does not make this clear, so I will get this updated.

Let me know if you have any questions.

Thanks,
JColvin

[eyz]

On 1/13/2021 at 6:49 PM, JColvin said:

Hi @eyz,

I apologize for the delay.

That line is in there for the IC1 and IC2 (the two schmitt triggers, https://www.onsemi.com/pub/Collateral/NL27WZ17-D.PDF, located prior to the N-FETs), as these ICs can only handle up to 5.5V from the host boards. If you leave JP1 disconnected (disconnecting the external power supply that can be applied to the separate J4 screw terminal from pin 6 on the 6-pin header), you can provide a 12V power supply and not hurt your board that way. I see that the reference manual does not make this clear, so I will get this updated.

Let me know if you have any questions.

Thanks,
JColvin

JColvin,

So, if JP1 is connected to the FPGA dev board (within < 5 V) on the JP1 VCC pin you can connect 12V/GND to JP4 without any potential voltage back through JP1, right? It's simply a concern of powering through JP1 > 5V, right?

[JColvin]

Hi @eyz,

Correct, as long as JP1 is disconnected so that any applied external power does not end up getting routed to the connected FPGA board, you'll be good to go.

You'll still need to keep the external voltage within voltage range and power limitations listed in the MOSFETs datasheet(https://www.onsemi.com/pub/Collateral/NTHD4508N-D.PDF) of course.

Let me know if you have any other questions.

Thanks,
JColvin