• 0

USB104A7 DDR3 backbone clock error issue



I'm trying to compile a design using USB104A7 board. The issue is with the DDR3L memory. It fails with the following issue.

Even after implementing the workaround suggested by Xilinx the error is the same.

[DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are MainDesign_i/clk_wiz_0/inst/clk_out1.

Clk1 -  166.667Mhz connected to sys_clk_i

clk2 -  200Mhz connected to clk_ref_i

Is there a working design that uses the DDR3L ram properly on this board. The OOB design feeds the clock directly from the on board crystal without a clocking wizard. Even following that design and adding a separate clocking wizard leads to the same issue.

Seems this comes from the hardware clock pin allocation. Any ideas how to resolve this.



Link to post
Share on other sites

3 answers to this question

Recommended Posts

  • 0

Hi @rmccormack1,

There's an not-yet-fully-released version of the board files that helps to fix it available here: https://github.com/Digilent/vivado-boards/archive/refs/heads/Microblaze-MIG.zip

The solution is to reconfigure the MIG to accept a 100 MHz system clock (avoiding the upstream clocking wizard entirely, and just connecting the system clock to the 100 MHz clock pin) and produce it's own reference clock. This also entails constraining the sys_clk_i port in an XDC and, in the case of the USB104, either tying off the sys_reset or connecting it to a button through an inverter manually.

I've attached a working Vivado 2020.1 project.




Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now