Berk Ata Özer Posted December 29, 2020 Share Posted December 29, 2020 Hello everyone, Im a electrical engineering student. I have a VHDL project. I really need to creat state machine and after Im gonna try to code on verilog. If anyone help, I would be very pleased. Merry Christmas, Have healthy days :) term_project_cs303_fall2020.pdf Link to comment Share on other sites More sharing options...
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Berk Ata Özer
Hello everyone, Im a electrical engineering student. I have a VHDL project. I really need to creat state machine and after Im gonna try to code on verilog. If anyone help, I would be very pleased. Merry Christmas, Have healthy days :)
term_project_cs303_fall2020.pdf
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