OK, I'm a newbie just trying to run a demo provided for my new Arty S7-25 board, specifically the Arty S7 General I/O Demo, and I'm quite frustrated. I think these demos are intended for newbies like myself, and as such, I expect them to run without a hitch. They don't.
I installed Vivado per the instructions given on the Installing Vivado, Vitis, and Digilent Board Files page. I then downloaded the zip file identified for my Arty S7-25 board and successfully installed it via the instructions given for Vivado (as opposed to SDK Hardware Handoff) on the Using Digilent Github Demo Projects page. I then tried to generate a bitstream and found it wouldn't complete due to the following errors.
I see the identified signals in the VHDL source...
The Arty-S7-25-Master.xdc file provided with the demo has a presumably incorrect comment at the top "## This file is a general .xdc for the Arty S7-50 Rev. B" and everything is commented out except the configuration options (BITSTREAM.CONFIG.CONFIGRATE 50, CONFIG_VOLTAGE 3.3, CFGBVS VCCO, BITSTREAM.CONFIG.SPI_BUSWIDTH 4, CONFIG_MODE SPIx4). Among those pins commented out, I see all the signals that caused errors except "CLK" (the xdc file has "CLK100MHZ" and "CLK12MHZ" but has no "CLK"). I also noted that the xdc file provided with the demo is not the same as the Arty-S7-25-Master.xdc file on GitHub. I decided not to try the GitHub file because the one included with the demo is presumably referenced in the demo's VHDL.
As an experiment, I uncommented the xdc lines for BTN[0], BTN[1], BTN[2], and BTN[3] then reran bitstream generation and got the same hard errors as before plus new errors for the uncommented lines saying "set_property expects at least one object" so it seems the VHDL isn't referencing the xdc file.
I'm now at a loss for what to do. Any suggestions (other than turning of DRC)?
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RodRico
OK, I'm a newbie just trying to run a demo provided for my new Arty S7-25 board, specifically the Arty S7 General I/O Demo, and I'm quite frustrated. I think these demos are intended for newbies like myself, and as such, I expect them to run without a hitch. They don't.
I installed Vivado per the instructions given on the Installing Vivado, Vitis, and Digilent Board Files page. I then downloaded the zip file identified for my Arty S7-25 board and successfully installed it via the instructions given for Vivado (as opposed to SDK Hardware Handoff) on the Using Digilent Github Demo Projects page. I then tried to generate a bitstream and found it wouldn't complete due to the following errors.
I see the identified signals in the VHDL source...
The Arty-S7-25-Master.xdc file provided with the demo has a presumably incorrect comment at the top "## This file is a general .xdc for the Arty S7-50 Rev. B" and everything is commented out except the configuration options (BITSTREAM.CONFIG.CONFIGRATE 50, CONFIG_VOLTAGE 3.3, CFGBVS VCCO, BITSTREAM.CONFIG.SPI_BUSWIDTH 4, CONFIG_MODE SPIx4). Among those pins commented out, I see all the signals that caused errors except "CLK" (the xdc file has "CLK100MHZ" and "CLK12MHZ" but has no "CLK"). I also noted that the xdc file provided with the demo is not the same as the Arty-S7-25-Master.xdc file on GitHub. I decided not to try the GitHub file because the one included with the demo is presumably referenced in the demo's VHDL.
As an experiment, I uncommented the xdc lines for BTN[0], BTN[1], BTN[2], and BTN[3] then reran bitstream generation and got the same hard errors as before plus new errors for the uncommented lines saying "set_property expects at least one object" so it seems the VHDL isn't referencing the xdc file.
I'm now at a loss for what to do. Any suggestions (other than turning of DRC)?
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