I am not at all experienced in FPGAs, the only thing I did is in ALTERA in bachelor studies course and recently the Xilinx Zybo board and made a LED blink or a full-adder examples.
I am however finding it difficult and frustrating to try to program the flash memory in the Zybo board to make my code non-volatile, after many trials and looking at other examples that do not describe this process step by step there is only ending up quitting.
i came across things like FSBL (First Stage Boot Loader), along with the bit stream from Vivado project, then i wanted to avoid the SDK by using only Vivado and exporting the hardware which requires other stuff like a block design which require other stuff like IP blocks and connecting things together that i have no idea about. It's an interconnected mess for me.
I would really appreciate someone who came across that and describe the process in simple details.
Sorry if i lack some basics, my aim at the end is to read a PWM signal (frequency and duty cycle) and produce them again by changing them e.g. input is 5 kHz and 90% and output from FPGA is 5 kHz and 60%, the FPGA should act as a duty cycle limiter.
My chip is: Zybo (xc7z010clg400-1) (picture attached)
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LaserMJ
Hello All,
I am not at all experienced in FPGAs, the only thing I did is in ALTERA in bachelor studies course and recently the Xilinx Zybo board and made a LED blink or a full-adder examples.
I am however finding it difficult and frustrating to try to program the flash memory in the Zybo board to make my code non-volatile, after many trials and looking at other examples that do not describe this process step by step there is only ending up quitting.
i came across things like FSBL (First Stage Boot Loader), along with the bit stream from Vivado project, then i wanted to avoid the SDK by using only Vivado and exporting the hardware which requires other stuff like a block design which require other stuff like IP blocks and connecting things together that i have no idea about. It's an interconnected mess for me.
I would really appreciate someone who came across that and describe the process in simple details.
Sorry if i lack some basics, my aim at the end is to read a PWM signal (frequency and duty cycle) and produce them again by changing them e.g. input is 5 kHz and 90% and output from FPGA is 5 kHz and 60%, the FPGA should act as a duty cycle limiter.
My chip is: Zybo (xc7z010clg400-1) (picture attached)
Software: Vivado 2018.1
Best regards,
MJ
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