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Zybo - Zynq Z-7010 Using Vivado 2018.1 and problems with the serial flash


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Hello All,

I am not at all experienced in FPGAs, the only thing I did is in ALTERA in bachelor studies course and recently the Xilinx Zybo board and made a LED blink or a full-adder examples.

I am however finding it difficult and frustrating to try to program the flash memory in the Zybo board to make my code non-volatile, after many trials and looking at other examples that do not describe this process step by step there is only ending up quitting.

i came across things like FSBL (First Stage Boot Loader), along with the bit stream  from Vivado project, then i wanted to avoid the SDK by using only Vivado and exporting the hardware which requires other stuff like a block design which require other stuff like IP blocks and connecting things together that i have no idea about. It's an interconnected mess for me.

I would really appreciate someone who came across that and describe the process in simple details.

Sorry if i lack some basics, my aim at the end is to read a PWM signal (frequency and duty cycle) and produce them again by changing them e.g. input is 5 kHz and 90% and output from FPGA is 5 kHz and 60%, the FPGA should act as a duty cycle limiter.

My chip is: Zybo (xc7z010clg400-1) (picture attached)

Software: Vivado 2018.1

Best regards,

MJ

20201226_141347.jpg

Edited by LaserMJ
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Hi 😄,

It seems there is very less activity on this forum, meanwhile i managed to solve this problem and I'd like to share my success.

In a short form this is what my work flow looks like:

------------- Vivado Part 😵 -------------

1) Create a project with the Zybo board

2) Import constraints file for Zybo and uncomment LEDs, Ports and buttons you need and don't forget the clk clock.

3) Import or write your VHDL or Verilog file (make sure to test your code before trying to upload it to the SPI Flash)

4) Create a Block Design and Add the ZYNQ7 Processing System block 

5) Run Connection automation and connect FCLK_CLK0 with M_AXI_GP0_ACLK

6) Right click your HDL code and select Add Module to Block Design

7) Right click each input and output of your RTL design and select Make Exernal

7) Rename each input and output on the RTL design to match the ports defined in the HDL design

8) Click on Validate design icon (F6) on the Block Diagram

9) Click on Generate Block Design from the left menu

10) Now Run Synthesis then Implementation then Generate Bit Stream (It take some minutes)

11) Go to File -> Export -> Export Hardware (Check Include Bitstrem)

12) Go to File -> Launch SDK (SDK will open automatically with your required design files added to it)

------------- SDK Part 🥴 -------------

13 ) design_1_wrapper_hw_platform_0 will be preloaded

14 ) Create a FSBL (First Stage Boot Loader) application. Go to File -> New -> Application Project

15 ) Name your project FSBL -> Next

16) Select Zynq FSBL and click on Finish

17) On the tree view menu right click FSBL project and select Create Boot Image (All required fields should be pre-loaded)

18) Click on Create Image

19) Click on the Xilinx menu from the tool -> Select Program Flash

20) Browse for your Image file found in "MyProject.sdk\FSBL\bootimage\BOOT.bin"

21) Browse for your FSBL file found in "MyProject.sdk\FSBL\Debug\FSBL.elf"

22) Click on Program and wait a while until everything looks okay in the message box.

Note: During programming the Flash make sure that your booting mode is JTAG then after programming the flash switch to SPI

23) Power cycle your Zybo board and your program shall now be loaded from the SPI Flash

24) 🤢 🤮

25) 😎 

Good luck Folks,

M

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