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Do JTAG-HS2/HS3 cables support 1.5 V signaling?


asmi

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I apologize for the long delay.

That is a typo in the table; the JTAG HS3 and JTAG HS2 (and similar products) only support a 1.8V through 5V range. I will make sure this table gets corrected; I imagine the error came from a mistype on a number pad.

Thanks,
JColvin

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Thanks for you response - delayed response is still infinitely better than no response at all.

It's a shame 1.5 V is not supported - I guess I will have to splash up for Xilinx official programmer. HS3 served me well over years, but it looks like it's time to move on.

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I will let our design engineers know that there is some interest for 1.5V signal support, in case that is something that can be relatively easily integrated into any future versions of the HSX products that might be made. I realize it'll be too little too late for you by then, but perhaps (if Digilent does make it) it will help somebody else.

Thanks,
JColvin

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34 minutes ago, JColvin said:

I will let our design engineers know that there is some interest for 1.5V signal support, in case that is something that can be relatively easily integrated into any future versions of the HSX products that might be made. I realize it'll be too little too late for you by then, but perhaps (if Digilent does make it) it will help somebody else.

Thanks,
JColvin

Thanks. I honestly kind of assumed that HSx support entire range of possible configuration voltages (which are 1.5, 1.8. 2.5 and 3.3 V), hence why I asked when noticed inconsistencies. 1.5 V is required for 7 series FPGAs if you need to use bank 14 (and maybe 15, depending on config mode) for DDR3, as it's the only way to reach required memory bandwidth in certain packages (like x32 for BGA-256, or SODIMM x64 for 484 or 676 package). It's not really a showstopper as it's possible to just add a few more level shifters onto such board (there will be some for QSPI Flash already, as 1.5 V versions of flash don't exist), but still adds more "stuff" in (usually) already densely populated area right around FPGA package.

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