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GPS design


damrr

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Hi,

i need to implement FPGA-based offline tracking system by parsing the GPS data using Verilog Hardware Description Language (Verilog HDL)

i have to display NMEA results from GPS receiver  through UART Port.  i have  no idea how to design using verilog.

 please help me.

 thanks in advance

 

 

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25 minutes ago, damodhar said:

i have  no idea how to design using verilog.

Step 1: Learn how to design using Verilog. If you don't like Verilog then VHDL is a good choice.

If step 1 is impractical, get a second job to pay someone who does know how to design using Verilog or VHDL to do the design for you. The problem here is that you have no control over how the design will be implemented and if you later want to add functionality or find that the original design isn't working for all use cases then you have to spend more money.

A worse approach would be for someone to hand you a generalized solution to your problem.

I'm pretty sure that the best approach for most people involves step 1, even if you hire a contractor to do the work.

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Sorry, I misinterpreted the main part of your question.

Generally, GPS devices use a simple UART interface, typically at 9600 baud. All you need is a decent Verilog UART module. If you've been doing Verilog for some time I'd be surprised if you haven't already written your own UART as an exercise. If you haven't then there are plenty around for free. After that it's just a matter of writing an interface to set the GPS device registers and read data that might have to be parsed. depending on what the specs are for your display of the data this could get involved but likely a simple state machine could work.  I suspect that perhaps the display presentation is more complicated a basic rendering of the raw data. The difficulty is usually in the details.

I'd start with the datasheet for the GPS device being used.

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Hi,

I have implemented gps to parsing nmea data from gps receiver through uart Interface.

But the problem is I am getting $gntxt  01,01,01 getting more than 100 frame errors and uart rx was disabled.

and one more thing is is there any way to do without using zync ultra scale processor.

Please check attached snapshots of block design and nmea format.

Thanks

IMG_20210102_220257.jpg

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