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Incorrect Schematic for ArtyS7


Patrick Lehmann

Question

In the board description for the ArtyS7, it's written to have a 12 MHz system clock at pin F14. That's not correct.

  1. Schematic revision E.1 for ArtyS7 is showing IC2 is open => no clock at all
  2. IC2 is - if soldered - a 100 MHz clock => ASEM1-100.000MHZ-LC-T
  3. As also discovered by the author of the board description, 12 MHz is a useless clock for 7-series FPGA,s because it's to slow for clock modifying blocks (PLL, MMCM, ...)
  4. The trace 12MHz/UCLK has a R0, but no source in schematics (incomplete schematics or an open trace ...)

As a summary: the ArtyS7 board has officially no system clock, only DDR3 reference clock can be used.

image.png

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Hi @Patrick Lehmann,

That is correct, there is not a 100 MHz system clock on the Arty S7. The flow recommended flow instead would be to use the 100 MHz DDR clock to drive the MIG system clock input and have the corresponding reference clock input on the MIG be driven by the ui_addn_clk_0 output that is on the MIG. This is described a little bit more in section 3 and 5 of the Arty S7 Reference Manual: https://reference.digilentinc.com/reference/programmable-logic/arty-s7/reference-manual.

Thanks,
JColvin

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