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Increase BRAM memory on Nexys Video


Zzingoh

Question

Hi All,

 

I am trying to increase the size of BRAM since the code segment in Vitis FW got overflowed by 30K

I googled the web and found I need to change the Range in Address Editor tab in Vivado.

 

1. In Address Editor tab, changed Range to 1M for data and 1M for instruction. Save

2. Validate board RTL and worked

 

but I can not increase up to 2M. I am getting error during validating board design. Look like 1M is maximum.

Would you please suggest how to increase code segment and data segment more than 1M?

Here is the error. 

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'Disable Collision Warnings(Disable_Collision_Warnings)' with value 'false' for BD Cell 'microblaze_0_local_memory/lmb_bram'. User configuration exceeds BRAM count in the selected device
INFO: [IP_Flow 19-3438] Customization errors found on 'microblaze_0_local_memory/lmb_bram'. Restoring to previous valid configuration.
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
ERROR: [BD 41-1273] Error running post_propagate TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
    ::xilinx.com_ip_blk_mem_gen_8.4::post_propagate Line 69
ERROR: [BD 41-241] Message from IP propagation TCL of /microblaze_0_local_memory/lmb_bram: set_property error: Validation failed for parameter 'Disable Collision Warnings(Disable_Collision_Warnings)' with value 'false' for BD Cell 'microblaze_0_local_memory/lmb_bram'. User configuration exceeds BRAM count in the selected device
Customization errors found on 'microblaze_0_local_memory/lmb_bram'. Restoring to previous valid configuration.

 

Thanks you

Tommy

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5 answers to this question

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If I change address range from Address Editor tab and then validate the design, there is no error and lscripts.ld in Vitis has 1M size range for code.

Do you think this method is incorrect? I can't see any size menu during microblaze automation. During automation, I can only select up to 128K this is so small

So I used Address Editor tab to change address range. and during validating a design, BRAM size is automatically populated with 1M value.

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Regardless of what the tools say your device has a total of 365 36K BRAMs, which works out to a total of 1495040 bytes available. These are spread out around the device so using all of them as one memory structure will present timing issues. 

I'd suggest that you accept the MicroBlaze as a limited use option for executing code. Rather than use up all of the device BRAM, using the external DDR might be better. If you want a higher performance processor then ZYNQ might be a better option, The best option might be connecting an FPGA to a cheap SBC like the Raspberry Pi 4.

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Thank you. 

Here is the snapshot of the address editor for my project. 

 

Based on your suggestion, code + data should be within 1Mb?

 

1. data

axi_gpio

axi_usblite

microblaze_local_memory_dlmb

microblaze_intc

spi_slave

vadj_control

 

2. Code

microblaze_local_memeory_ilmb

 

Also, do you know how to set up heap and stack for Vitis application? Does they reside in data segment?

 

Thanks,

 

 

 

Screenshot 2020-12-14 201209.png

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I'm not the one who should be answering these questions as I don't use MicroBlaze. In the exceedingly rare cases where I feel the need to uses a soft-processor in an FPGA design I'd use a very small, very efficient, very low resource hogging core, and with limited functionality. Because of the way that most ZYNQ boards are designed I wouldn't even try to run anything but a highly targeted, stripped-down, bare-bones subset of Linux on those platforms much less a full blown distribution. In my opinion, if you need more than 64K of code and data segments for an application requiring a soft-processor then perhaps you should investigate a different approach.

That's just my perspective and I realize that it isn't a universal one. 

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