Arty7-100 DDR3 MMCM problem

[ach]

I have an UART & a  DDR3 controller on an Arty 7 -100 board. The UART talks to minicom.

Hello world worked, then I dont know what I changed but now I get the error below. .

I then started a completely new project and that one works fine without the error. So I went back to the previous project

and tried reset_synth and it still fails. Both the IDE diagrams look the same, use the same xdc file.

What do I need to do to fix this error.

 

[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 333.333 MHz (CLKIN1_PERIOD, net pll_clk3) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y1 (cell design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (24.000000), multiplication factor CLKFBOUT_MULT_F (8.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

[DRC PDRC-43] PLL_adv_ClkFrequency_div_no_dclk: The computed value 666.667 MHz (CLKIN1_PERIOD, net clk_out2) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X1Y1 (cell design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i) falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1600.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (6.000000), multiplication factor CLKFBOUT_MULT_F (4) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

[asmi]

1 hour ago, ach said:

I dont know what I changed but now I get the error below. .

What you need to do is to find out what did you change, and next time think before making changes.

That said, if you messed with MIG there is a known issue with the wizard when it doesn't properly recall the frequency it's set to right here (the screenshot is from the different board, but the field is the same):

 

You need to make sure this field is set to 166.667 MHz. Once you fix it, keep clicking "next" until the end of the wizard and then regenerate everything.

The bad news? You will have to do it every single time you run the MIG wizard to completion. The good news? You probably shouldn't ever launch this wizard, especially until you will know what are you doing. Create a diagram, drag MIG from the board components window, and leave it alone.

[ach]

On 12/4/2020 at 1:26 PM, asmi said:

What you need to do is to find out what did you change, and next time think before making changes.

That said, if you messed with MIG there is a known issue with the wizard when it doesn't properly recall the frequency it's set to right here (the screenshot is from the different board, but the field is the same):

 

You need to make sure this field is set to 166.667 MHz. Once you fix it, keep clicking "next" until the end of the wizard and then regenerate everything.

The bad news? You will have to do it every single time you run the MIG wizard to completion. The good news? You probably shouldn't ever launch this wizard, especially until you will know what are you doing. Create a diagram, drag MIG from the board components window, and leave it alone.

 

[ach]

Thanks. Yes you are correct, I really do not know what I am doing or what I changed. Before your reply on Dec 4 I started from scratch i.e. I took an arty 100 reference design and added stuff to it and it was all fine. Made good progress. Then I screwed around with some custom IP (changed a reset to a ~reset) on a test pattern generator. That got things all messed up. Then regenerating messed up the mig with the above error again (after 3 weeks). Now, I have

sys_clock into the mig 166.667 MHz, ref_clk 200 MHz and in the mig clock period 3.225ps freq = 310.08 MHz. Now in the freq screen the closest to 166.67 MHz in my design I get 165.371 MHz. Should this be fine? Also, can you point me to a document which tells me how I should use this --

i have an external clock at 100 MHz going to a clock generator outputing 200 MHz to ref clock and 166.667 to sys_clock. Now, here too the clock gen says cannot generate 1666.667 MHz but seems to be fine. And the output of the mig clock goes to the rest of the system.