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Arty7-100 DDR3 Controller Stays in reset


ach

Question

Hi,

This is using vivado 2019.2

I have reset going into active low sync_reset of the MIG generating a DDR3 for the arty 100 board. sys_reset which is active low is connected to the board reset pin C2 which is normally high but goes low when pressed. ui_clk_sync_rst is only connected to ex_reset_in of the Processor System Reset whose output mb_reset goes to the microblaze.

I also have a UART connected to a serial port on a linux terminal (using minicom). Program is not doing memory for now, just a hello world to the uart via a print. When I first build it and run it I see "hello world" on the terminal. Pressing the red reset button does not restart the processor to print out another "hello world".

Now, here I am using 2020.1

For comparison, I have another design without a ddr3 controller where the external reset from the board is directly connected to the Processor System Reset pin ex_reset_in (active low as it is directly connected to pin C2. In this case, when I press the red reset button, the processor gets reset and I get the "hello world" appearing again. So the external pin does a reset and the program starts again.

Then I tried simulating the ddr3 design. I tried two things,

Attempt A below hich is supposed to be correct, ui_clock is low, then toggles for say 16 cycles and then goes low. mmcm_locked always low, init_claib_complete always x and ui_clk_sync_reset is always 1. This was supposed to work. However, I tried Attempt B below.

Attempt B I see mmcm_locked go to 1, ui_clock toggles and ui_clk_sync_reset is always 1. init_calib_complete goes from X to 0.

Some how I think the DDR3 reset  output is not correct. This is on a arty 7-100 board.

Any help is appreciated. Thanks Arun

///////////////////////////////////////

`timescale 1ns / 1ps

module test();

reg clk = 0;
reg my_reset;
   
design_1_wrapper uut(
    .sys_clock(clk),
    .reset(my_reset)
    );
    
initial begin
   // #200 is 200 ns which is 200/5 = 40 cycles

/* Attempt A
 my_reset = 1;
 #100
 my_reset = 0;
 #100
 my_reset = 1;
*/

// Attempt B

 my_reset = 0;
 #100
 my_reset = 1;
 #100
 my_reset = 0;

end

always
    #5 clk <= ~clk;    
    
endmodule

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