UART not working on Nexys4DDR

[Tota]

I am trying to get UART working on my Nexys4DDR board.

I coded in systemverilog the receiver circuit; 1 start bit, 8 data bit, 1 stop bit with no parity.  I have BAUD_RATE set at 115200 and frequency at 100MHz. I am checking everything at half way through (frequency/BAUD_RATE). For the wrapper, the LEDs should light on depending on what byte is sent. I have a working testbench.

For the PC side, I am using pyserial to send the data. I don't get any error and everything shows that it is sending the data from the PC side. However, the LEDs don't light on.

I attached the code I wrote with a working testbench.

Also, LED 20 lights on indicating that the FPGA is receiving data from the UART port.

hello.sv hello_tb.sv hello_test.py nexys4.xdc uart_receiver.sv

[Tota]

Never mind, I had a latch in uart_receiver.sv in line 60 which was preventing valid from going to 1 for 1 cycle. I should have checked the reports before programming the FPGA. I thought verilator would have detected the latch so I didn't check Xilinx reports.