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I have trouble instantiating a MIG and using the DDR on the NetFPGA SUME board.

In the acceptance test, the init_calib_complete goes high, however I cannot recreat it in vivado 2020.1

The sources my configurations were based on:

NetFPGA SUME live repository's multiple projects

OSNT SUME live repository's extmem project 

Tapasco project.


Additionally as the vc709 is similar, I have taken a look on the followings:





However, I have tried multiple configurations and none of them worked.

Could somebody point me into the right direction?

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