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NetFPGA SUME DDR


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Hi,

I have trouble instantiating a MIG and using the DDR on the NetFPGA SUME board.

In the acceptance test, the init_calib_complete goes high, however I cannot recreat it in vivado 2020.1

The sources my configurations were based on:

NetFPGA SUME live repository's multiple projects

OSNT SUME live repository's extmem project 

Tapasco project.

 

Additionally as the vc709 is similar, I have taken a look on the followings:

https://www.youtube.com/watch?v=0KnvW_6Bgu0&ab_channel=XilinxInc

https://www.xilinx.com/support/documentation/boards_and_kits/vc709/2014_4/xtp235-vc709-mig-c-2014-4.pdf

https://github.com/Xilinx/HLx_Examples/tree/master/Acceleration/tcp_ip/scripts/VC709/DRAM

 

However, I have tried multiple configurations and none of them worked.

Could somebody point me into the right direction?

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