Transmission of Non-MIPI camera sensor data (i.e. any monochrome sensor) using MIPI CSI-2 TX Controller Ip core from on one Arty7 Board to another Arty7 board as MIPI CSI-Rx system or any MIPI Receiver based Video processor.
IP core Application:
The Xilinx MIPI CSI-2 TX Controller implements camera sensor transmitter interface over MIPI D-PHY Interface. It can be used to bridge between non-MIPI camera sensors to MIPI based video processor. This Core provides combination of MIPI CSI-2 transmit controller and D-PHY interface.
System Overview as per our understanding:
· After power on, Clock generator IP core generates different clock required for FPGA subsystems. (Status : Working)
· FPGA configures camera sensor by providing appropriate commands via I2C Interface.(Status : Working)
· After successful configuration, Sensor generates PSYNC (Pixel Clock), HSYNC (Line Clock), VSYNC (Frame clock) and 14-bit video data which are input to FPGA. (Status : Working)
· Since sensor provides Non-MIPI output signals and Xilinx MIPI CSI-2 Tx doesn’t have monochrome RAW data input, one complete control system required in FPGA which convert these sensors output signals in to MIPI CSI-2 TX Core compatible data and control signals. (Status : How to give above signals to this IP core, After implementing required logic we are not getting any output on this IP core)
· MIPI CSI-2 Tx controller core has In-built physical layer which generated D-PHY outputs. (Status : Not outputs on D-PHY)
· D-PHY output can be accessible to another Arty-7 board as MIPI CSI-2 Rx or any MIPI based video processor to perform further post-processing.
· Above description is given in block diagram and sensor waveform
· Sensor specification: image resolution 384 x 288 @ 30 FPS with 14 bit RAW video data.
Problem faced: sensor provides Non-MIPI output signals and Xilinx MIPI CSI-2 Tx doesn’t have monochrome RAW data input, So we are not able generate any D-PHY output after configuration. No examples related to RAW data of 8 or 14 bit.
Question
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Objective:
Transmission of Non-MIPI camera sensor data (i.e. any monochrome sensor) using MIPI CSI-2 TX Controller Ip core from on one Arty7 Board to another Arty7 board as MIPI CSI-Rx system or any MIPI Receiver based Video processor.
IP core Application:
The Xilinx MIPI CSI-2 TX Controller implements camera sensor transmitter interface over MIPI D-PHY Interface. It can be used to bridge between non-MIPI camera sensors to MIPI based video processor. This Core provides combination of MIPI CSI-2 transmit controller and D-PHY interface.
System Overview as per our understanding:
· After power on, Clock generator IP core generates different clock required for FPGA subsystems. (Status : Working)
· FPGA configures camera sensor by providing appropriate commands via I2C Interface.(Status : Working)
· After successful configuration, Sensor generates PSYNC (Pixel Clock), HSYNC (Line Clock), VSYNC (Frame clock) and 14-bit video data which are input to FPGA. (Status : Working)
· Since sensor provides Non-MIPI output signals and Xilinx MIPI CSI-2 Tx doesn’t have monochrome RAW data input, one complete control system required in FPGA which convert these sensors output signals in to MIPI CSI-2 TX Core compatible data and control signals. (Status : How to give above signals to this IP core, After implementing required logic we are not getting any output on this IP core)
· MIPI CSI-2 Tx controller core has In-built physical layer which generated D-PHY outputs. (Status : Not outputs on D-PHY)
· D-PHY output can be accessible to another Arty-7 board as MIPI CSI-2 Rx or any MIPI based video processor to perform further post-processing.
· Above description is given in block diagram and sensor waveform
· Sensor specification: image resolution 384 x 288 @ 30 FPS with 14 bit RAW video data.
Problem faced: sensor provides Non-MIPI output signals and Xilinx MIPI CSI-2 Tx doesn’t have monochrome RAW data input, So we are not able generate any D-PHY output after configuration. No examples related to RAW data of 8 or 14 bit.
References:
1. MIPI CSI Controller Subsystems –
https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html#overview
2. MIPI CSI-2 Transmitter Subsystem V2.1 -
https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_tx_subsystem/v2_1/pg260-mipi-csi2-tx.pdf
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