Hello everyone, I am very grateful to you, i always get help through this forum
I am implementing a simple example of loopback test in ZCU111 (a signal 2.655 GHz from DAC229_T1_CH0 to ADC225_T1_CH0). It is an external connection using SAM cable. The objective will be that the input of the DAC will be almost equals to the output of the ADC. I am using an ILA which is connected directly to the ADC data stream. The clock of ILA connected to m0_axis_aclk_0. The probes are connected the output data axi stream.
I am very grateful if any person can help me. The output of the DAC is quite different of the input of the ADC. Please see the screenshots containing the DAC configurations. I will need to mention that I have used clocks wizard in my design.
The output of clock wizard is connected to input axi stream of DAC s1_axis_aclk_0, the input of clock wizard is connected the output clock of the DAC clk_dac1_0.
Another clock wizard in which it input is connected to the output axi stream of the ADC m0_axis_aclk_0 and the output of this clock wizard is connected to the output clock of the ADC clk_adc0_0. Another clock wizard in which it input is connected to the output axi stream of the ADC m0_axis_aclk_0 and the output of this clock wizard is connected to the output clock of the ADC clk_adc0_0.
Question
jean
Hello everyone, I am very grateful to you, i always get help through this forum
I am implementing a simple example of loopback test in ZCU111 (a signal 2.655 GHz from DAC229_T1_CH0 to ADC225_T1_CH0). It is an external connection using SAM cable. The objective will be that the input of the DAC will be almost equals to the output of the ADC. I am using an ILA which is connected directly to the ADC data stream. The clock of ILA connected to m0_axis_aclk_0. The probes are connected the output data axi stream.
I am very grateful if any person can help me. The output of the DAC is quite different of the input of the ADC. Please see the screenshots containing the DAC configurations. I will need to mention that I have used clocks wizard in my design.
The output of clock wizard is connected to input axi stream of DAC s1_axis_aclk_0, the input of clock wizard is connected the output clock of the DAC clk_dac1_0.
Another clock wizard in which it input is connected to the output axi stream of the ADC m0_axis_aclk_0 and the output of this clock wizard is connected to the output clock of the ADC clk_adc0_0. Another clock wizard in which it input is connected to the output axi stream of the ADC m0_axis_aclk_0 and the output of this clock wizard is connected to the output clock of the ADC clk_adc0_0.
ila_1 ila_ADC (
.clk(m1_axis_aclk_0), // input wire clk
.probe0(m10_axis_0_tdata[15:0]), // input wire [15:0] probe0
.probe1(m10_axis_0_tdata[31:16]), // input wire [15:0] probe1
.probe7(m10_axis_0_tdata[127:112]), // input wire [15:0] probe7
.probe8(m11_axis_0_tdata[15:0]), // input wire [15:0] probe8
.probe9(m11_axis_0_tdata[31:16]), // input wire [15:0] probe9
……………………….…………………………………………………………………………………………
.probe15(m11_axis_0_tdata[127:112]), // input wire [15:0] probe15
.probe16(m11_axis_0_tvalid), // input wire [0:0] probe16
.probe17(m10_axis_0_tvalid) // input wire [0:0] probe17
);
For the input, I have a two ROM, one contains I data, the other Q data
Assign ROM[0]=-16'd16084;assign ROM[1]=-16'd24126;assign ROM[2]=16'd16083;assign ROM[3]=-16'd8042;assign ROM[4]=16'd32167…………………………………………..
Assign ROM2[0]=16'd8041;assign ROM2[1]=16'd8041;assign ROM2[2]=16'd8041;assign ROM2[3]=16'd8041;assign ROM2[4]=16'd32167;assign ROM2[5]=-16'd24126;assign ROM2[6]=16'd32167;assign ROM2[7]=16'd32167
assign s10_axis_0_tdata[31:0] = {ROM2[cpt],ROM[cpt]}; .............. assign s10_axis_0_tdata[255:224] = {ROM2[cpt+7],ROM[cpt+7]};
The input of DAC works at the clock s1_axis_aclk_0(AXI stream input data).
Link to comment
Share on other sites
0 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.