Hello! I'm currently making a HDMI based FPGA project, and I am currently using the DVI2RGB IP cores. The problem that I'm having is that, when simulating using Vivado 2019.1, the VDE, VSYNC, HSYNC signals are all low, and the 24 bit output data is all 0's, even when valid TMDS signals are being sent to the IP. The IP is working as the pLocked signal is high when running the simulation.
I saw somewhere, I believe it was the official documentation or a forum post, that the output would be like mine, with all low signals, when the data streams are not synchronized. I'm wondering if the IP is not able to be simulated without a large amount of time, as my simulation would take 60-80 hours real time per 1 second of simulated time. I also saw in a forum post around 4 years ago that the synchronization would take 5-15 seconds, so simulating for me would be absurdly long. So far, I've simulated around 500ms of time with no change from the IP outputs.
Is this normal for this IP core? Would it be best to move the design straight to hardware to test instead of simulating in Vivado?
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mtober
Hello! I'm currently making a HDMI based FPGA project, and I am currently using the DVI2RGB IP cores. The problem that I'm having is that, when simulating using Vivado 2019.1, the VDE, VSYNC, HSYNC signals are all low, and the 24 bit output data is all 0's, even when valid TMDS signals are being sent to the IP. The IP is working as the pLocked signal is high when running the simulation.
I saw somewhere, I believe it was the official documentation or a forum post, that the output would be like mine, with all low signals, when the data streams are not synchronized. I'm wondering if the IP is not able to be simulated without a large amount of time, as my simulation would take 60-80 hours real time per 1 second of simulated time. I also saw in a forum post around 4 years ago that the synchronization would take 5-15 seconds, so simulating for me would be absurdly long. So far, I've simulated around 500ms of time with no change from the IP outputs.
Is this normal for this IP core? Would it be best to move the design straight to hardware to test instead of simulating in Vivado?
Thank you.
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