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DVI2RGB IP Core Simulation


mtober

Question

Hello! I'm currently making a HDMI based FPGA project, and I am currently using the DVI2RGB IP cores. The problem that I'm having is that, when simulating using Vivado 2019.1, the VDE, VSYNC, HSYNC signals are all low, and the 24 bit output data is all 0's, even when valid TMDS signals are being sent to the IP. The IP is working as the pLocked signal is high when running the simulation.  

I saw somewhere, I believe it was the official documentation or a forum post, that the output would be like mine, with all low signals, when the data streams are not synchronized. I'm wondering if the IP is not able to be simulated without a large amount of time, as my simulation would take 60-80 hours real time per 1 second of simulated time. I also saw in a forum post around 4 years ago that the synchronization would take 5-15 seconds, so simulating for me would be absurdly long. So far, I've simulated around 500ms of time with no change from the IP outputs. 

Is this normal for this IP core? Would it be best to move the design straight to hardware to test instead of simulating in Vivado?

Thank you. 

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56 minutes ago, mtober said:

Would it be best to move the design straight to hardware to test instead of simulating in Vivado?

As you've discovered, it's possible to try and simulate some designs over an unrealistic time period. Even if you were to try running a simulation for "60-80 hrs" ( I'm betting that you've underestimated the actual time due to OS constyraints) the amount of data generated would render normal simulation tools unusable for reviewing the results. Sometimes you can change the simulation resolution from ps to ns and speed things up. Sometimes you can work out ways to speed-up or bypass initialization periods ( DDR calibration is an example ) Sometimes you can't do any of these things. For video, requiring high resolution and large amounts of data you will likely have to get creative about verification. This might be a case where cycle based simulation, if you are using Verilog/Verilator is an acceptable option. Otherwise, you will have to go right to hardware and use either ILA instantiations and or custom debug logic in your design.  

Sometimes you have to get creative. Remember, the best debug tool available to you lies between your ears and just behind your eyes.

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