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'Hello World' Tutorial with Vivado 2020.1 and Vitis to run on Nexys A7-100T


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Hi,

Where can I find a tutorial to run 'Hello World' with Vivado 2020.1 and Vitis to run on Nexys A7-100T ?

I've searched everywhere, including this forum, and couldn't find a tutorial. 

I tried a tutorial on YouTube for the Artix 7, and I'm unable to generate a bitstream.

I get this critical warning:

[Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port reset_0 can not be placed on PACKAGE_PIN C12 because the PACKAGE_PIN is occupied by port reset. Please note that for projects targeting board parts, user LOC constraints cannot override constraints provided with the board. ["c:/Users/curti/XilinxProjectsCurtis/HelloWorld_hw/HelloWorld_hw.srcs/sources_1/bd/HelloWorld_design/ip/HelloWorld_design_rst_clk_wiz_1_100M_0/HelloWorld_design_rst_clk_wiz_1_100M_0_board.xdc":3]

 

And I get these errors:

[DRC NSTD-1] Unspecified I/O Standard: 2 out of 8 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: diff_clock_rtl_clk_n, and diff_clock_rtl_clk_p.

[DRC UCIO-1] Unconstrained Logical Port: 3 out of 8 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: reset_0, diff_clock_rtl_clk_n, and diff_clock_rtl_clk_p.

 

I'm a new user of Vitis, and relatively new to Vivado. Can anyone offer suggestions on how to correct the errors?

Or, better yet, where can I find a tutorial that works to run 'Hello World' with Vivado 2020.1 and Vitis to run on Nexys A7-100T ?

My thanks in advance for any suggestions,

Curtis

 

Edited by CurtisNotestine
Clarification for the specific warning.
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Hi @CurtisNotestine,

Are you following a 'Hello World' design in particular? For the 2020.1 version of the Xilinx tools, I usually direct users to the guides the Digilent has on our Wiki here: https://reference.digilentinc.com/reference/programmable-logic/guides/start.

The errors you are getting imply that the .xdc file does not have the proper pins uncommented and named correctly. Are you using HDL or a Block Design flow? If you are using a Block Design flow, did you install the Digilent board files for the Nexys A7 100T?

Thanks,
JColvin

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25 minutes ago, JColvin said:

Are you following a 'Hello World' design in particular?

Yes, I found this one:   Lec89 - Demo: Microblaze processor on FPGA. (I'll paste the link in the next reply.)

It is targeted for a Basys 3 board. I thought it would work.

 

 

24 minutes ago, JColvin said:

Are you using HDL or a Block Design flow?

I'm using the IP block design flow.

Yes, I installed the Digilent board file for the Nexys A7 100T. It works successfully for my HDL designs.

 

30 minutes ago, JColvin said:

The errors you are getting imply that the .xdc file does not have the proper pins uncommented and named correctly.

I see what's going on: The IP block design is calling for a differential clock. I modified clk_whiz_1 from a differential clock to a single line. 

 

6 hours ago, JColvin said:

Are you following a 'Hello World' design in particular? For the 2020.1 version of the Xilinx tools, I usually direct users to the guides the Digilent has on our Wiki here: https://reference.digilentinc.com/reference/programmable-logic/guides/start.

Thanks, I'll try the Getting Started with Vivado IP Integrator and Vitis, even though I would like to get the 'Hello World' to work.

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