Synchronizing DigitalDiscovery pods in pattern generation mode for >16 driven signals

[gdchun]

I think this will work for logic analyzer operations (use a common input for trigger) but what about >16 signals for pattern generation?  In my application for reading/writing an SRAM, I need to:

1. generate 18 bits of address

2. One of these combinations: 

    - 33 signals: 18 address, 8 data, 4 byte enables, 3 controls

    - 39 signals: 18 address, 16 data, 2 byte enables, 3 controls

    - 45 signals: 18 address, 32 data, 1 byte enable, 3 controls

Any of these combinations would appear to need 3 DigitalDiscovery pods to do this - I believe the same 3 pods could also be used in logic analyzer mode to read the memory

I understand you can synchronize logic analyzer pods with a common input signal line

Question: If it is possible, how do you synchronize pods for pattern generation (drive >16 outputs) ?