Zynq 7000 UART local loopback mode

[Takun]

Dear all,

I am tranning interface with UART, so in the Zynq-7000 SoC the Technical Reference Manual it have a UART local loopback mode and I want to make ones. 

https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

Has anyone done it yet, please show me how to make on vivado and vitis.

I have finished building UART 0 (MIO 10 MIO11) on vivado to make hardware file. But I do not know how to do next.

I am using Vivado & Vitis 19.1 version and Zybo Z20 board

 

[fpga_123]

On 10/22/2020 at 8:07 PM, Takun said:

Dear all,

I am tranning interface with UART, so in the Zynq-7000 SoC the Technical Reference Manual it have a UART local loopback mode and I want to make ones. 

https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

Has anyone done it yet, please show me how to make on vivado and vitis.

I have finished building UART 0 (MIO 10 MIO11) on vivado to make hardware file. But I do not know how to do next.

I am using Vivado & Vitis 19.1 version and Zybo Z20 board

 

Hi,

You may want to have a look at the UART examples provided in C:\Xilinx\SDK\2019.1\data\embeddedsw\XilinxProcessorIPLib\drivers\scugic_v3_10\examples.

Xilinx provides examples to work with polled mode, local echo mode and the interrupt mode.

 

Bests,