50 MHz clock

[Tim.O]

I'm trying to generate 25 MHz clock from 100 MHz (Basys3, Vivado19) in a code below. But, it seems it is 50 MHz  

Multiplying 100 by 8 and divide it by 2, and divide it again by 16, then I though CLKFXDV is 25MHz. What is wrong? 

DCM_CLKGEN_INST1 : DCM_CLKGEN
   generic map (
      CLKFX_MULTIPLY      => 8,         -- Multiply value - M - (2-256)
      CLKFX_DIVIDE            => 2,         -- Divide value - D - (1-256)
      CLKFXDV_DIVIDE       => 16,        -- CLKFXDV divide value (2, 4, 8, 16, 32)
      CLKFX_MD_MAX        => 4.0,       -- Specify maximum M/D ratio for timing analysis
      CLKIN_PERIOD           => 10.0,     -- Input clock period specified in nS
      SPREAD_SPECTRUM => "NONE", 
      STARTUP_WAIT         => FALSE   -- Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
   )
   port map (
      CLKIN     => clk100_buffered,         -- 1-bit input: Input Master clock
      CLKFX     => clk400_unbuffered,    -- 1-bit output: Generated clock output
      CLKFX180  => open,                        -- 1-bit output: Generated clock  output 180 degree out of phase from CLKFX.
      CLKFXDV   => clk025_unbuffered, -- 1-bit output: Divided clock output

      -- Ports for dynamic phase shift
      PROGDONE  => open,         -- 1-bit output: Active high output to indicate the successful re-programming
      PROGCLK     => '0',              -- 1-bit input: Clock input for M/D reconfiguration
      PROGDATA   => '0',              -- 1-bit input: Serial data input for M/D reconfiguration
      PROGEN       => '0',              -- 1-bit input: Active high program enable
      STATUS        => open,         -- 2-bit output: DCM_CLKGEN status   

      FREEZEDCM => '0',             -- 1-bit input: Prevents frequency adjustments to input clock
      LOCKED        => open,        -- 1-bit output: Locked output
      RST               => '0'              -- 1-bit input: Reset input pin
   );
 

Best regards.

[JColvin]

Hi @T.O,

It looks like you're using some clocking features (DCM_CLKGEN) from Spartan-6 devices that no longer work or are unreliable with 7-series devices as per pages 22 and 23 of UG472 from Xilinx. You'll instead want to use a MMCM and/or PLL to create this clock. There are examples of both in the Language Templates within Vivado or you can use the Clocking Wizard IP.

Let me know if you have any questions.

Thanks,
JColvin

[Tim.O]

> looks like you're using some clocking features (DCM_CLKGEN) from Spartan-6 devices that no longer work or are unreliable with 7-series devices

I see. I did not know it... (;_;)

Thank you very much for your comments. I will check it ”Templates within Vivado”