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Voltage Levels in Nexys A7 Master Constraint File


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The master constraint file for the Nexys A7 sets voltage levels for all pins to LVCMOS33 *except* pins T8, and U8, which are connected to switches SW[8] and SW[9], respectively.  These two pins are set to LVCMOS18 instead.

Is there any reason why these to pins are not set to LVCMOS33 voltage levels?  When using the switches to input a multiple-bit input this causes an error when synthesizing in Vivado.

Thanks!

Edited by JNestor
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Hi @JNestor,

The reason that SW8 and SW9 (T8 and U8) are set to LVCMOS18 rather than 3.3V CMOS is because those two pins are connected to Bank 34 which contains all of the pin connections for the DDR2 chip which operates at 1.8V. Banks can only be set a single voltage, so the switches are stuck being at 1.8V CMOS rather than 3.3V like the rest of their friends.

Does Vivado create an actual error that prevents bitstream generation or is it a type of warning instead?

Thank you,
JColvin

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Hi, @JColvin,

Thank you for your response - that explains the difference in the constraints. 

I went back a re-checked, and you are correct; it only generates a warning, not an error.  For example, if I create a 4-bit input named "bus_in" and connected it to switches 12-15 I get the following warning:

image.thumb.png.a2775dd4deff91986099ddf6bb6ace53.png

However, since input bus is just connected to switches switches and not to an actual bus, this difference in I/O standards should not be a problem.

Thanks,

JNestor

 

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2 hours ago, JNestor said:

However, since input bus is just connected to switches switches and not to an actual bus, this difference in I/O standards should not be a problem.

Perhaps you just chose your words badly but it's important to assign the correct IOSTANDARD to every pin used in a design. Use the schematic to see which IO bank each pin that you are using is connected to. The schematic will show what the bank Vccio voltage is associated with each pin and therefore constrain your selection of IOSTANDARD assignment for that pin. Furthermore, if you want the design to work properly the IOSTANDARD assignment must be compatible with the logic family that the pin is connected to. Ensuring compatibility is not only important for ensuring that a design will work but failing to do so might cause damage to the FPGA, especially when connecting user interfaces to FPGA pins. Not all logic selections for a given Vccio are compatible. Consult the Series 7 Select IO User's Guide for information. 

Bottom line is that warnings and errors involving IOSTANDARD must be resolved by the designer as they represent a big red flag that a part of the design was not performed properly.

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