The master constraint file for the Nexys A7 sets voltage levels for all pins to LVCMOS33 *except* pins T8, and U8, which are connected to switches SW[8] and SW[9], respectively. These two pins are set to LVCMOS18 instead.
Is there any reason why these to pins are not set to LVCMOS33 voltage levels? When using the switches to input a multiple-bit input this causes an error when synthesizing in Vivado.
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JNestor
He
The master constraint file for the Nexys A7 sets voltage levels for all pins to LVCMOS33 *except* pins T8, and U8, which are connected to switches SW[8] and SW[9], respectively. These two pins are set to LVCMOS18 instead.
Is there any reason why these to pins are not set to LVCMOS33 voltage levels? When using the switches to input a multiple-bit input this causes an error when synthesizing in Vivado.
Thanks!
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