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Zybo Z7-20 MIPI connector and netic19 question


I have two questions concerning my Zybo Z7-20 board.

Question 1:
According to the Zybo-Z7 2018 reference manual, the MIPI port has a 15 pin connector. Page 28, reference manual shows the connector labels as:

Pin #     Function Zybo Z7          Connection Details
1            GND                             GND
2            MIPI CSI-2 Lane 0 (-)  Terminated and connected to 2 FPGA pins asdescribed in XAPP894
3            MIPI CSI-2 Lane 0 (+)  Terminated and connected to 2 FPGA pins as described in XAPP894
4            GND                              GND
5            MIPI CSI-2 Lane 1 (-)   Terminated and connected to 2 FPGA pins as described in XAPP894
6            MIPI CSI-2 Lane 1 (+)  Terminated and connected to 2 FPGA pins as described in XAPP894
7            GND                             GND
8            MIPI CSI-2 Clock (-)   Terminated and connected to 2 FPGA pins as described in XAPP894
9            MIPI CSI-2 Clock (+)   Terminated and connected to 2 FPGA pins as described in XAPP894
10           GND                            GND
11           GPIO                           Direct Connection to FPGA
12           GPIO                           Direct Connection to FPGA
13           SCL                             Direct Connection to FPGA, with 1.5 KOhm Pull-up
14           SDA                             Direct Connection to FPGA, with 1.5 KOhm Pull-up
15           3V3                               3.3 V Power rail

The zybo constraints files has the MIPI port having 16 connectors. In particular, the the constraint name of pin 16 maps to pin 14 of the reference manual, Other pins are in the same boat. Plus there is no 3.3 V rail in the constrains file.

pin -  #set_property INTERNAL_VREF 0.6 [get_iobanks 35]
pin 1  #set_property -dict { PACKAGE_PIN J19   IOSTANDARD HSUL_12     } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n
pin 2  #set_property -dict { PACKAGE_PIN H20   IOSTANDARD HSUL_12     } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p
pin 3  #set_property -dict { PACKAGE_PIN M18   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]
pin 4  #set_property -dict { PACKAGE_PIN L19   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]
pin 5  #set_property -dict { PACKAGE_PIN L20   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]
pin 6  #set_property -dict { PACKAGE_PIN J20   IOSTANDARD HSUL_12     } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]
pin 7  #set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVDS_25     } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n
pin 8  #set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVDS_25     } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p
pin 9  #set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]
pin 10 #set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]
pin 11 #set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVDS_25     } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]
pin 12 #set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVDS_25  } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]
pin 13 #set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk
pin 14 #set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33     PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio
pin 15 #set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl
pin 16 #set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda

So, part 1.a: Can you help me resolve the difference in MIPI definitions between the reference manual and the constraints file?
      part 1.b: Can pins 11-14 (reference manual) or pins 13-16 (constraints) be used a general IO
(we have run out of IO on the Zybo development board and are looking for any IO we can find)  
Question 2:
The Zybo constraints file indicate there are 12 netic19 ports. Where are these pins located on the Zybo Z7-20 board?
Can they be used as general IO?

##Unconnected Pins (Zybo Z7-20 only)
#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13
#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13
#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13
#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13
#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13
#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13
#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13
#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13
#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13
#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13
#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13
#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13

Many thanks in advance. Any help is greatly appreciated.

Cheers, R

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Hi @rzsmi,

The listed order of pins on a constraint file does not matter, so long as the required pins being declared are present, that's all that is needed.

As for the discrepancy in pins, .xdc files don't list GND and 3.3V connections, only connections to GPIO and clock lines. As noted in the reference manual, some of the individual pins on the MIPI CSI-2 connector are actually connected to two separate FPGA pins as per XAPP894.

If you count all of those doubled up pins and other "single" GPIO pins, you will note they add up to the same 16 pins that are listed in the .xdc file. You can see what extra pins they are connected to on page 2 of the Zybo Z7 schematic.

Let me know if you have any questions.


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Hi JColvin,

Thank-you for your reply.

The 12 pins I am referring are listed at the as the last items in the Zybo .xdc file. They are seen on ZyboZ7_schematic page 11/14 as part of BANK 13. V10 for example is listed on page 11/14 as V10 (IO_L21N_T3_DQS_13) and netic19_v10 in the .xdc file, but don't see any connectors related to V10 on the ZyboZ7_20 board. Can these be accessed?


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