• 0

why a clock frequency of an IP presents it sampling frequency and it banud rate


Question

Hello every body, I have a stupid question. I dont know when any IP is connected to a clock. It sampling freqeuncy correspond to it clock and it baund rate correspond aslo the input clock.  example dds compiler clocked at 30 MHz, baud rate is 30Mbit/s and the sampling frequency is 30 Mega hertz. An IFFT also. Thanks for any clarification 

Link to post
Share on other sites

5 answers to this question

Recommended Posts

  • 0
2 hours ago, jean said:

Hello every body, I have a stupid question. I dont know when any IP is connected to a clock. It sampling freqeuncy correspond to it clock and it baund rate correspond aslo the input clock.  example dds compiler clocked at 30 MHz, baud rate is 30Mbit/s and the sampling frequency is 30 Mega hertz. An IFFT also. Thanks for any clarification 

@[email protected] Please sir, have any idea.

Link to post
Share on other sites
  • 0

Hi @jean,

I'm not sure I understand your question. Are you wanting to know different aspects of an IP in general are occurring at different frequencies? And how to know if an IP is connected to a clock or not?

Thanks,
JColvin

Link to post
Share on other sites
  • 0
7 hours ago, JColvin said:

I'm not sure I understand your question. Are you wanting to know different aspects of an IP in general are occurring at different frequencies? And how to know if an IP is connected to a clock or not?

Thanks,
JColvin

Hi Colvin, First of all, thank you for your feedback. In fact, I have a confusion between baud rate, clock rate, sampling freqency of a general way of an IP in FPGA. How to know the sampling frequency, clock rate, baud rate (data rate) of an IP. These terms are related to the clock at which the IP is connected.  For example if I have an IP cloked at 100MHz, 100 MHz correspond the sampling frequency, the baud rate also correspond to 100Mbit/s or  I should  know each sample is coded in bits? It can be a stupid question but these terms block me. How to know them of any IP xilinx.  Please JColvin, can you explain me. Thanks you.

Link to post
Share on other sites
  • 0

@jean,

Your definitions are all over the place.

The sample rate is the rate at which an ADC produces samples, or a DAC consumes them.  This is defined by your hardware.

The clock frequency doesn't have to be equal to the sample rate.  It's often easier when it is.  If not, the clock rate can easily be faster than the sample rate.  If the sample rate needs to be faster than the clock rate, then you'll need to process multiple samples in parallel.  While doable, most IP cores are designed for one sample per clock or less.  Building a design to handle more than one sample per clock will take some serious design work.

Baud rate is an entirely different concept.  The baud rate of a communications system is the rate at which it sends data symbols.  Those data symbols will contain at least one bit of information (such as with BPSK or BFSK systems), but may contain many more bits of information.  Some modems as I recall were sending 10 bits per baud.  To satisfy Nyquist, the baud rate *must* be less than half the sample rate.  A common requirement is that the sample rate must be at least four times the baud rate.

I'm not sure what you mean by the DDS compiler having a "baud rate" associated with it, unless you are trying to build some form of frequency shift keyed system such that the DDS accepts one input per baud.  Personally, were I you, I'd dump the DDS compiler and replace it with a simple table lookup.  From there you can control the phase going into your table.  You can then control phase your way, rather than trying to understand how the DDS compiler is controlling its phase internally.

As I have said before, I'm not sure the Xilinx signal processing IP's are going to work for your application--where your sample rate is eight times more than your clock rate.  You may have to build your own signal processing IP's--to include any sine/cosine generation and/or FFTs.

Dan

Link to post
Share on other sites
  • 0
4 hours ago, [email protected] said:

@jean,

Your definitions are all over the place.

The sample rate is the rate at which an ADC produces samples, or a DAC consumes them.  This is defined by your hardware.

The clock frequency doesn't have to be equal to the sample rate.  It's often easier when it is.  If not, the clock rate can easily be faster than the sample rate.  If the sample rate needs to be faster than the clock rate, then you'll need to process multiple samples in parallel.  While doable, most IP cores are designed for one sample per clock or less.  Building a design to handle more than one sample per clock will take some serious design work.

Baud rate is an entirely different concept.  The baud rate of a communications system is the rate at which it sends data symbols.  Those data symbols will contain at least one bit of information (such as with BPSK or BFSK systems), but may contain many more bits of information.  Some modems as I recall were sending 10 bits per baud.  To satisfy Nyquist, the baud rate *must* be less than half the sample rate.  A common requirement is that the sample rate must be at least four times the baud rate.

I'm not sure what you mean by the DDS compiler having a "baud rate" associated with it, unless you are trying to build some form of frequency shift keyed system such that the DDS accepts one input per baud.  Personally, were I you, I'd dump the DDS compiler and replace it with a simple table lookup.  From there you can control the phase going into your table.  You can then control phase your way, rather than trying to understand how the DDS compiler is controlling its phase internally.

As I have said before, I'm not sure the Xilinx signal processing IP's are going to work for your application--where your sample rate is eight times more than your clock rate.  You may have to build your own signal processing IP's--to include any sine/cosine generation and/or FFTs.

Dan

@[email protected] Thanks you very much sir for these details. I am very for grateful you.  I'm sorry for the inconvenience and my differnt questions. I am a beginner and this  is  my first project in FPGA. I hope that over time, I will be a good FPGA engineer

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now