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Pmod DA3 interface with Basys 3 in Verilog


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Hello I am creating a verilog module on the basys 3 board to interface with the Pmod DA3. I have tried running the module with the DA3 connected and wasn't getting any voltage reading. I have my sclk speed at 25Mhz. Below is my current code and screenshots of my test bench and the pmod outputs on an oscilloscope. Any help is appreciated.

 

`timescale 1ns / 1ps

module sclk(
    input clock,
    input reset,
    output sclk
    );
    
    reg[24:0] count = 0;
    reg sclk = 0;
    
    always @ (posedge clock or posedge reset) begin
        if (reset ==1'b1)begin
            count <= 0;
            sclk <= 0;
        end else begin
            count <= count + 1;
            if(count == 1) begin 
                sclk <= ~sclk;
                count <= 0;  
            end
        end 
    end      
endmodule

__

`timescale 1ns / 1ps

module spi0(
    input clock,
    input reset,
    input send,
    output sclk0,
    output reg cs,
    output reg ldac,
    output reg din
    );
    
    reg[15:0] data [3:0];
    reg[15:0] count;
    reg [1:0] sel;
     
    sclk sclk_inst (
        .clock(clock),
        .reset(reset),
        .sclk(sclk0)    
    ); 
    
    initial begin
    data[0] = 16'b0101111000010101;
    data[1] = 16'b1000011111100001;
    count = 16'd16;
    cs = 1;
    sel = 0;
    end
    
    always @ (negedge sclk0 & send == 1)begin
            if (send == 1)begin
                if ( count > 0)begin
                    cs = 0;
                    ldac = 0; 
                end
                if (count == 0)begin
                    cs = 1;
                    ldac = 1;
                    count = 16'd16;     
                end        
                
            din = data[sel][count-1];
            count = count - 1;
            end
    end       
endmodule

__

`timescale 1ns / 1ps

module spi0_testbench();
    reg clock = 0;
    reg reset = 0;
    reg send = 0;
    reg [50:0]counter = 0;
    reg [16:0] i;
    
    wire sclk0;
    wire cs;
    wire ldac;
    wire din;
    wire[15:0] count;
    
    spi0 UUT(clock, reset, send, sclk0, cs, ldac, din);
   
    always @ (*)begin
    #10    
        if (i >= 127 & i < 129)begin
            send = 0;
        end
        if (i < 127 | i >= 129) begin
            send = 1;
        end 
        if (i < 127)begin
        end   
    end
    
    initial begin
        for (i = 0; i < 1000; i = i + 1)begin
            clock = ~clock;
            counter = counter + 1; 
            #1;
        end
    end 
endmodule

 

Capture00.PNG

thumbnail_IMG_7825.jpg

Green: SCLK

Yellow: DIN

Blue: CS

Pink: LDAC

Edited by pgpsn
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Welcome to the forums!

`[email protected](negedge sclk0 & send == 1)` is likely to be causing problems.

First, you are already preventing the process's logic from happening by wrapping the contents of the process in an `if (send == 1)`, making the `send==1` redundant. Additionally, I'm not positive what the `&` ends up actually representing. Avoid mixing clocks and other signals in sensitivity lists.

Second, sclk0 is generated in logic, and cannot be routed on the dedicated clock lines of the FPGA. I'd recommend using the `posedge clock` here, with an additional flag to enable the logic.

 

Edit: On a second look, it appears that the polarity of the LDAC signal is also flipped. Refer to the timing diagram on page 5 of the AD5541A's datasheet. LDAC needs to pulse low while CS is high, at least ten ns after CS goes high.

A coworker also pointed out that you can just not drive LDAC at all, and the pulldown resistor on the DA3 will let data go directly from the input register to the DAC latch.

Thanks,

Arthur

Edited by artvvb
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