Zedboard: Getting started in Vivado


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I have recently bought a Zedboard and as a complete and utter beginner I thought I'd start with the Digilent tutorial, https://reference.digilentinc.com/vivado/getting_started/v2019.2 . I got as far as trying to edit the constraint file Zedboard-Master.xdc as in Section 6.7. The master files are in https://github.com/Digilent/digilent-xdc/archive/master.zip?_ga=2.2696439.638022708.1602322154-505626126.1588185805

At that point I got stuck: the tutorial says the clock port will be at the top of the xdc file and followed by a create_clock line. However, the clock port isn't at the top and there is certainly no create_clock line. I assume the GCLK line is the clock port I need, but what do I do about the create_clock line?

I'm baffled because the other boards in the digilent-xdc-master.zip all seem to match the tutorial in having a clock port at the top of the file, followed by a create_clock statement. My copy of the Zedboard-Master.xdc was last corrected in June 2016.

Thanks
 

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Hi @tt12345678,

This is because Digilent did not create the Zedboard .xdc file that is present on the Digilent GitHub; Avnet did. We did not change this file to the Digilent styled format in the interest of maintaining compatibility with official Zedboard material that exists in various places (on Avnet's website, zedboard.org, etc.).

The clock line is on line 82 on the Zedboard .xdc. You can then add your own create_clock statement after it if you want to; I'd probably use the same one listed in the Zybo Z7 xdc files on line 9 (https://github.com/Digilent/digilent-xdc/blob/master/Zybo-Z7-Master.xdc).

Other tutorials that we have, such as the Getting Started with Vivado IP Integrator guide (link), will automatically take care of the clock creation for you in the Zynq preset.

Let me know if you have any questions.

Thanks,
JColvin

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Hi @JColvin

Thanks very much for your answer, it's very helpful. In the meantime, I've been going through some of the Zynq Book tutorials. They seem pretty good, although it's a bit of a challenge getting some of them to work in Vitis 2020.1, which seems to have some bugs in the IP creation bit. I suppose coming across problems improves understanding in the long run.

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Hi @tt12345678,

Yes, some of Vivado IPs have changed over the years and versions, especially since 2015.1 so upgrading them to newer versions can be tricky. For what it's worth though, Digilent has a set of materials for working with Vivado/Vitis 2020.1 available here: https://reference.digilentinc.com/reference/programmable-logic/guides/start.

Thanks,
JColvin

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