Resetting a reg count n repeat case loop

[Sonia]

when my clock has been switched to a higher frequency, I need to repeat the case loop again. However, I have an issue to reset my count to 0 and repeat the loop again while maintaining the higher clock frequency. So how do I solve this issue?

Below are the conditions I used:

always @ (posedge myclk) begin

     clkout <= (out_count == 5)? slowfclk : slowclk;

end

always @ (posedge clkslt) begin

     out_count <= (out_count == 5)? 5: out_count + 1; 

     case(out_count):

.........

[zygot]

2 hours ago, Sonia said:

So how do I solve this issue?

The solution to your problem is identical to one encountered in software development. In instead of using 'magic numbers' in your code use abstraction. In regular software you can reference a calculated constant or variable. In Verilog or VHDL you can use generics or parameters. A simple way in VHDL is to define your count as different constants each calculated for a specific clock rate. A better way is to use the IEEE.Math library and calculate the value as a constant and reference that in your code. If you use a generic for the clock rate this is handled for you during synthesis. I'm mentioning VHDL because I use it more, but Verilog has the same built in capabilities.

HDL design isn't software development but that doesn't mean that you can't apply good software practice techniques to improve your HDL development methods.