How do I get the PMods into the block diagram for an Arty S7?

[LenR]

When I create a block diagram for the Arty S750 I add a MicroBlaze then after running the wiz I add each of the items listed under Board. When I get to the PMods it says it can't do it because there is no possible options to connect. How do I add the PMods?

[JColvin]

Hi @LenR,

Which version of Vivado are you using? If you haven't seen it, we have a guide for using Pmods in Vivado and Vitis for the 2020.1 version of the Xilinx software available here: https://reference.digilentinc.com/reference/programmable-logic/guides/getting-started-with-pmod-ips. This guide also address how to handle the reset mentioned in your other thread.

Let me know if you have any questions about this.

Thanks,
JColvin

[LenR]

I'm using 2020.1 and I followed the guide, Neither of the links to the files at the beginning of the reference work, but I just went to the gethub site and picked them up there. I think it will solve most of the problems but it created a new one. There was a bunch of critical warnings that basically requires a board descriptor revision of 1.1 and both my S725 and s750 are at a level of 1.0. I have tried updating the revision, but it is stuck at 1.0.

After closing the project and starting another just to see if that would let the board descriptor update, I came back to the project and even though the descriptors are the same I don't see anymore warnings about that. It is complaining about removing a redundent IBUF and it could not create a IBUF_LOW_PWR constraint because it was not connected to a top level port, and CRITICAL WARNING: [Netlist 29-160] Cannot setproperty 'IOSTANDARD'. because the property does not exist for objects of type 'pin' ...design_1mig_7series_0_0.xdc:264  and also :265. That sort of problem has been dogging me for a couple of days.

One of my PMods is the I2S2, any idea when it will be supported?

Another potential problem is that the mig_7series_0 has a device temperature input I made it external as I could see no way to delete it.

When I Generate a Block Design, even though it says it is going to create four products it doesn't I am assuming that is because it hit a critical warning. The only designs I have been able to finish are without external memory.

[JColvin]

Hi @LenR,

I apologize; I didn't recall that the 2020.1 version of the Vivado IP library is in it's own branch here: https://github.com/Digilent/vivado-library/tree/v2020.1. As noted at the top of the guide, not all of the materials, in particular for the Pmod IPs have been updated for 2020.1.

I am confused about the comment about board descriptor saying it needs to be 1.1. Vivado will give critical warnings about Pmod IPs being packaged for different boards rather than the Arty S7, but all of those critical warnings can be safely ignored.

The Arty S7 boards have different clock requirements compared to other boards. After adding the DDR interface the board tab (described in the "Adding a DDR Interface" dropdown in the guide I linked), you will need to connect the ui_addn_clk_0 on the automatically generated mig_7series_0 IP to the clk_ref_i input. The ddr_clock on the Board tab will need to be connected to the sys_clk_i input on the mig_7series_0; if you already added the system clock from the board tab in conjunction with the clocking wizard, you can add in the DDR Clock by deleting the System Clock input and the existing Clocking Wizard, and then adding the DDR Clock to a new clocking wizard. Delete the newly created Clocking Wizard (unless you plan on using different clock frequencies in your design) and connect the ddr_clock to the sys_clk_i input on the mig_7series_0. Similarly, connect the reset pin that was added earlier in the tutorial to the sys_rst on the mig_7series_0 IP, and delete the inverter that was created earlier (presuming the guide was followed). Your block design will look similar to this one:

Quote

The device_temp_i[11:0] input can be left alone; I believe the board file for the Arty S7 50 is going to be updated to pre-configure the MIG so Vivado does not have any pop-up about this input.

With regards to Pmod IPs I do not know if the Pmod I2S2 will be turned into an IP core; I know there is a demo available for it here: https://github.com/Digilent/Pmod-I2S2.

Let me know if you have any questions.

Thanks,
JColvin

[LenR]

I would say there is sufficient difference between the S7 and the pmod doc that it could use it's own doc. I started a new project and used your modifications one interesting thing that happened was the board sources display quit showing the ddr_clock input as used, but the block diagram shows it and validates ok. 

I did get those critical warnings about the board revision and the critical warning about the mig_7series_0 device temp not used. I know if I make it external that one will go away, but am stumped about the rest. 

[LenR]

Just to see what would happen, I went ahead inspite of the "Critical Warnings" and ran the Synthesis and when that completed with no problems, I ran the implementation, then the Generate Bitstream which also appeared to work. I got another warning from Synthesis about timing violations during setup and there were some other warnings earlier which I have included. I will try to find out as much about these warnings as possible and fix them if I can. Some it may turn out I can ignore, but the each of these look like they could be a problem.

When I generated the system after creating the Mig7 setup you showed me in your last post, the system clock attached to the clock output from the Mig7, which I didn't expect.

The warning about the D-cache looks like some device access may be outside the cache, I don't know if that is a problem or not, but maybe I totally misinterpreted the message.

The warning about the Encoder Pmod looks like it would not accept configuration, but maybe that is intentional, I don't know.

It looks like I may be able to include the last couple of items on the board and that will just about fill up the S750. I hope to create a hardware configuration that I can program without having to regenerate the hardware again. I am under the impression that the Webpack version (I am currently using a one month eval of the full software) does not allow MicroBlaze configuration with external memory which is what I assume the DDR3 is. I would love to be wrong, but in any case I want to get as much out of this month as I can. I have tons yet to learn, but feel like progress is being made. Thank you very much.

[LenR]

Another question, I didn't include the Quad SPI Flash because I assumed that would only be needed in the design if I was going to use it in a program and that the initialization of the FPGA is something the board handles and no additional software is needed. Please tell me if I need to include it for that to work. Thanks.

[LenR]

Forgot the screen cap of the timing violation on implementation.

[JColvin]

Hi @LenR,

You can keep using the WebPACK version with Microblaze and external memory in Vivado 2020.1 for free.; the vast majority of us at Digilent use the free WebPACK versions of Vivado without detriment.

The Critical Warnings screenshot you posted about how different IPs were packaged with a different board value can all be safely ignored. Vivado is just letting you know that those IPs were created with when a different system board was selected, but the IPs themselves are designed to be board agnostic.

The guide I linked before, https://reference.digilentinc.com/reference/programmable-logic/guides/getting-started-with-pmod-ips, has the system clock connected to the MIG because that is how most of the non-Zynq based Digilent boards are set up. For whatever reason, the Arty S7 is set up differently, though changes are being made to it's board files so that it is a little more user friendly.

You don't need to include the Quad SPI Flash unless you intend on using that non-volatile storage (such as for storing a Vitis project).

The timing diagram certainly has a lot of negative slack. What all extra connections are you attempting to add to the Arty S7 50 design? It looks like you have the Pmod OLEDrgb, two Pmod ENC, and a UART IP?

[LenR]

My goal is to create a music synthesizer, the two ENC are for menu traversal, the OLED is to display the menu and the uart will connect a USB to a MIDI input and output. I need to add the I2S2 and I have an I2C and SIO for various attached devices. I don't know if all will be needed, but I am also seeing what I can cram into an S750. Push it until it cries uncle so to speak. I am also interested in porting Forth as close to the hardware as I can, in which case I may not need the Microblaze, but I think the approach I am taking will get me learning the system, its strengths and weaknesses as fast as possible. If you have any suggestions about learning materials I would certainly welcome them. You have already been a tremendous help, I would have never figured out the clock stuff without your assistance.

What exactly does the negative slack mean, is there a document that covers this?

I am a retired systems engineer and it is great fun to work on this stuff without deadline pressure. My biggest problem is keeping it affordable and if the Webpack can handle it I think I have found a fine target. When I was in college getting my degree in Engineering Math and Computer Systems at the University of Central Florida, the early eight bit processors were coming into existence and we were learning on mini computers. The best course I had started with toggling a boot loader into a mini computer and building the system up to sample delay lines and plot out waveforms. When we left the class after three quarters we felt we knew what a computer was. My first real job at Harris Corp was to build an automatic inking system for big offset web printing presses, the kind that print magazines. It was a lot of work and a great success. We used a high level language called PLM at a time everyone else in the company was using assembly or even machine code on microprocessors. We used the micro like a mini. When we started up the finished project there was a line of pressmen watching and their hair literally stood on end. It was like an automatic pilot on an airplane, it allowed the pressman to do his job faster and pay attention to other details of starting up a print run that might last for days. It allowed them to cut paper waste from around 15,000 wasted copies to 1500. Huge. Another job was for a manufacturing line for contact lenses for J&J Vistacon. Lots of interesting jobs but the schedule pressure took a lot of the fun out of it. The great part was that I had to constantly learn new systems and software and get paid for it.

[JColvin]

Hi @LenR,

As a number of other far more experienced users than myself on this forum will tell you, implementing your design in hardware directly rather than using Microblaze or some other processor will be the best way to streamline the resource usage on a FPGA. Depending on your setup, you might be able to get away with only using one Pmod ENC, using the onboard switch to indicate if rotating the encoder is for vertical or horizontal scrolling on a menu and use the integrated push button as your selection/confirmation button.

Negative slack is Vivado's way of showing if the design meets timing (I'm not able to find a specific document covering it). My understanding is that slack indicates the difference between the required length of time it takes a signal to get from one place to another on the design vs how fast Vivado/"the tools" can get the signal from location A to location B. There is a Xilinx forum thread that illustrates this a bit more here: https://forums.xilinx.com/t5/Timing-Analysis/Negative-slack-causes-hold-violation/td-p/749460.

I did manage to create a design (not using all of the components you mentioned though) that successfully met timing; I didn't do anything beyond generating the bitstream but have attached a picture of the end block design.

Thanks,
JColvin

[RodRico]

On 10/7/2020 at 3:20 PM, LenR said:

I am also interested in porting Forth as close to the hardware as I can... I am a retired systems engineer and it is great fun to work on this stuff without deadline pressure. 

Same here. I used to sell a complete Forth environment (FORTH-79 plus editor, debugger, 8088 assembler, floating point, and real time priority preemptive multi-tasker). I literally just finished reviewing my 1988 source files to remind myself what minimum primitives (done in 8088 assembly) would be required to port over the FORTH words and vocabularies that build on them. I'm also a retired systems engineer with a background in radar development now retired and working without deadline pressure. A FORTH CPU will be an excellent way to dive in I think. Keep us informed!