Using an SPI device with ARTY board

[davec]

Hi,

I am using an original ARTY board ver C.  I have a microblaze with ethernet, memory, etc, which is a design that I have used on other projects.  I now added a quad_axi_spi board component with SPI port J6.  My code is based on the Xilinx \embeddedsw\XilinxProcessorIPLib\drivers\spi_v4_4\examples.

I can get the SPI to successfully transfer data in LOOPBACK mode but when I run without loopback, with a scope I do not see the SCLK move on pin 3 of SPI connector J6 at all.  When I look inside the FPGA, it looks like the SCLK is routed to the correct pin (F1).  The board file has the correct FPGA pins specified.  I have used the SPI flash with bootloader in the past, but not including SPI flash yet in this design until I can make J6 SPI work.  Ultimately I want to control an LMX2592 PLL chip.  Ehternet and serial UART both work in this design. 

Are there any examples or hints for using SPI on J6 with ARTY in this way? Am i doing something obviously wrong?

Thanks

  Dave

[artvvb]

Hi @davec

I don't see anything wrong with your hardware design or the board files. So I spun up a similar design with port J6, working from the polled_example (Vivado/Vitis 2020.1 and version 4.6 of the xspi drivers). Debugging the modifications showed a problem where XSpi_Transfer was silently failing when checking if a slave was selected in the driver, and finding none. Make sure you are calling XSpi_SetSlaveSelect. See my main.c, below.

#include "xspi.h"
#include "xparameters.h"
#include "xil_printf.h"
#include "sleep.h"
int main() {
	xil_printf("Hello World!\r\n");
	XSpi device;
	XSpi_Config *pcfg;
	pcfg = XSpi_LookupConfig(XPAR_AXI_QUAD_SPI_0_DEVICE_ID);
	XSpi_CfgInitialize(&device, pcfg, pcfg->BaseAddress);

	XSpi_SetOptions(&device, XSP_MASTER_OPTION);
	XSpi_Start(&device);
	XSpi_IntrGlobalDisable(&device);
	XSpi_SetSlaveSelect(&device, 0b1);

	u8 bytes [4] = {0xDE,0xAD,0xBE,0xEF};
	while (1) {
		XSpi_Transfer(&device, bytes, NULL, 4);
		usleep(1);
	}
}

Hope this helps,

Arthur

[davec]

Thank you, Arthur!  I actually discovered this just before I read your email.  When I realized I wasn't actually specifying the slave device, I punched it into the SPI_SSR during a breakpoint and that didn't work.  When I saw someone's example that called XSpi_SetSlaveSelect, the clock (and select line) started to work.  What threw me was that in the example, they run in loopback mode and they don't need to bother with setting the slave select.  It was hard to find an example that used external pins (and not loopback).  Next, I have to add a second SPI device, so I guess I need to add a constraint to specify which pin the new SS will come out on.  Can I use a GPIO, or will there be a conflict?- I am never quite sure how Vivado reads the board file pin locations.

Thanks again, Arthur.

  Dave

[artvvb]

Hi Dave,

The board files lock in the some of the IP settings. The number of slaves can't be changed when using the board files to constrain the SPI bus, since the board.xml interface and the part0_pins.xml constraints only specify a single chip select pin. 

I'd recommend using Make External on the relevant pins of the AXI Quad SPI's SPI port, and constraining them all yourself. For what its worth, it looks like clearing the interface selection to Custom in the IP's Board tab will preserve all of the other settings. It may also be necessary to manually add IO buffers into the design (probably in an RTL module between the AXI SPI core and the block design ports) as I'm not positive if Vivado will automatically insert the right buffers for the single tristate, multiple i/o pin pattern of the SS bus.

Alternatively, if wasting resources isn't an issue, you could just add a second AXI SPI controller.

-Arthur

[ghelbig]

I'm using an Arty A7-100 and I'm seeing something strange in the board file.

The CK_SS line - SS on J6 - connects to pin C1 in the schematic.  It is set to V17 in the board file.

The SPI CS does show up on Arduino IO-10.  This is pin V17 on the schematic.

The board file has"shield_dp0_dp19_tri_i_10" wired to "C1".

I think that these are reversed?